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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5define void @andn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {6; CHECK-LABEL: andn_v16i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vld $vr0, $a1, 09; CHECK-NEXT: vld $vr1, $a2, 010; CHECK-NEXT: vandn.v $vr0, $vr0, $vr111; CHECK-NEXT: vst $vr0, $a0, 012; CHECK-NEXT: ret13entry:14 %v0 = load <16 x i8>, ptr %a015 %v1 = load <16 x i8>, ptr %a116 %v2 = xor <16 x i8> %v0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>17 %v3 = and <16 x i8> %v2, %v118 store <16 x i8> %v3, ptr %res19 ret void20}21 22define void @andn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {23; CHECK-LABEL: andn_v8i16:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vld $vr0, $a1, 026; CHECK-NEXT: vld $vr1, $a2, 027; CHECK-NEXT: vandn.v $vr0, $vr0, $vr128; CHECK-NEXT: vst $vr0, $a0, 029; CHECK-NEXT: ret30entry:31 %v0 = load <8 x i16>, ptr %a032 %v1 = load <8 x i16>, ptr %a133 %v2 = xor <8 x i16> %v0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>34 %v3 = and <8 x i16> %v2, %v135 store <8 x i16> %v3, ptr %res36 ret void37}38 39define void @andn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {40; CHECK-LABEL: andn_v4i32:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vld $vr0, $a1, 043; CHECK-NEXT: vld $vr1, $a2, 044; CHECK-NEXT: vandn.v $vr0, $vr0, $vr145; CHECK-NEXT: vst $vr0, $a0, 046; CHECK-NEXT: ret47entry:48 %v0 = load <4 x i32>, ptr %a049 %v1 = load <4 x i32>, ptr %a150 %v2 = xor <4 x i32> %v0, <i32 -1, i32 -1, i32 -1, i32 -1>51 %v3 = and <4 x i32> %v2, %v152 store <4 x i32> %v3, ptr %res53 ret void54}55 56define void @andn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {57; CHECK-LABEL: andn_v2i64:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vld $vr0, $a1, 060; CHECK-NEXT: vld $vr1, $a2, 061; CHECK-NEXT: vandn.v $vr0, $vr0, $vr162; CHECK-NEXT: vst $vr0, $a0, 063; CHECK-NEXT: ret64entry:65 %v0 = load <2 x i64>, ptr %a066 %v1 = load <2 x i64>, ptr %a167 %v2 = xor <2 x i64> %v0, <i64 -1, i64 -1>68 %v3 = and <2 x i64> %v2, %v169 store <2 x i64> %v3, ptr %res70 ret void71}72