322 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5define void @vavg_b(ptr %res, ptr %a, ptr %b) nounwind {6; CHECK-LABEL: vavg_b:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vld $vr0, $a1, 09; CHECK-NEXT: vld $vr1, $a2, 010; CHECK-NEXT: vavg.b $vr0, $vr0, $vr111; CHECK-NEXT: vst $vr0, $a0, 012; CHECK-NEXT: ret13entry:14 %va = load <16 x i8>, ptr %a15 %vb = load <16 x i8>, ptr %b16 %add = add <16 x i8> %va, %vb17 %shr = ashr <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>18 store <16 x i8> %shr, ptr %res19 ret void20}21 22define void @vavg_h(ptr %res, ptr %a, ptr %b) nounwind {23; CHECK-LABEL: vavg_h:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vld $vr0, $a1, 026; CHECK-NEXT: vld $vr1, $a2, 027; CHECK-NEXT: vavg.h $vr0, $vr0, $vr128; CHECK-NEXT: vst $vr0, $a0, 029; CHECK-NEXT: ret30entry:31 %va = load <8 x i16>, ptr %a32 %vb = load <8 x i16>, ptr %b33 %add = add <8 x i16> %va, %vb34 %shr = ashr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>35 store <8 x i16> %shr, ptr %res36 ret void37}38 39define void @vavg_w(ptr %res, ptr %a, ptr %b) nounwind {40; CHECK-LABEL: vavg_w:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vld $vr0, $a1, 043; CHECK-NEXT: vld $vr1, $a2, 044; CHECK-NEXT: vavg.w $vr0, $vr0, $vr145; CHECK-NEXT: vst $vr0, $a0, 046; CHECK-NEXT: ret47entry:48 %va = load <4 x i32>, ptr %a49 %vb = load <4 x i32>, ptr %b50 %add = add <4 x i32> %va, %vb51 %shr = ashr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>52 store <4 x i32> %shr, ptr %res53 ret void54}55 56define void @vavg_d(ptr %res, ptr %a, ptr %b) nounwind {57; LA32-LABEL: vavg_d:58; LA32: # %bb.0: # %entry59; LA32-NEXT: vld $vr0, $a1, 060; LA32-NEXT: vld $vr1, $a2, 061; LA32-NEXT: vadd.d $vr0, $vr0, $vr162; LA32-NEXT: vsrai.d $vr0, $vr0, 163; LA32-NEXT: vst $vr0, $a0, 064; LA32-NEXT: ret65;66; LA64-LABEL: vavg_d:67; LA64: # %bb.0: # %entry68; LA64-NEXT: vld $vr0, $a1, 069; LA64-NEXT: vld $vr1, $a2, 070; LA64-NEXT: vavg.d $vr0, $vr0, $vr171; LA64-NEXT: vst $vr0, $a0, 072; LA64-NEXT: ret73entry:74 %va = load <2 x i64>, ptr %a75 %vb = load <2 x i64>, ptr %b76 %add = add <2 x i64> %va, %vb77 %shr = ashr <2 x i64> %add, <i64 1, i64 1>78 store <2 x i64> %shr, ptr %res79 ret void80}81 82define void @vavg_bu(ptr %res, ptr %a, ptr %b) nounwind {83; CHECK-LABEL: vavg_bu:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vld $vr0, $a1, 086; CHECK-NEXT: vld $vr1, $a2, 087; CHECK-NEXT: vavg.bu $vr0, $vr0, $vr188; CHECK-NEXT: vst $vr0, $a0, 089; CHECK-NEXT: ret90entry:91 %va = load <16 x i8>, ptr %a92 %vb = load <16 x i8>, ptr %b93 %add = add <16 x i8> %va, %vb94 %shr = lshr <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>95 store <16 x i8> %shr, ptr %res96 ret void97}98 99define void @vavg_hu(ptr %res, ptr %a, ptr %b) nounwind {100; CHECK-LABEL: vavg_hu:101; CHECK: # %bb.0: # %entry102; CHECK-NEXT: vld $vr0, $a1, 0103; CHECK-NEXT: vld $vr1, $a2, 0104; CHECK-NEXT: vavg.hu $vr0, $vr0, $vr1105; CHECK-NEXT: vst $vr0, $a0, 0106; CHECK-NEXT: ret107entry:108 %va = load <8 x i16>, ptr %a109 %vb = load <8 x i16>, ptr %b110 %add = add <8 x i16> %va, %vb111 %shr = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>112 store <8 x i16> %shr, ptr %res113 ret void114}115 116define void @vavg_wu(ptr %res, ptr %a, ptr %b) nounwind {117; CHECK-LABEL: vavg_wu:118; CHECK: # %bb.0: # %entry119; CHECK-NEXT: vld $vr0, $a1, 0120; CHECK-NEXT: vld $vr1, $a2, 0121; CHECK-NEXT: vavg.wu $vr0, $vr0, $vr1122; CHECK-NEXT: vst $vr0, $a0, 0123; CHECK-NEXT: ret124entry:125 %va = load <4 x i32>, ptr %a126 %vb = load <4 x i32>, ptr %b127 %add = add <4 x i32> %va, %vb128 %shr = lshr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>129 store <4 x i32> %shr, ptr %res130 ret void131}132 133define void @vavg_du(ptr %res, ptr %a, ptr %b) nounwind {134; LA32-LABEL: vavg_du:135; LA32: # %bb.0: # %entry136; LA32-NEXT: vld $vr0, $a1, 0137; LA32-NEXT: vld $vr1, $a2, 0138; LA32-NEXT: vadd.d $vr0, $vr0, $vr1139; LA32-NEXT: vsrli.d $vr0, $vr0, 1140; LA32-NEXT: vst $vr0, $a0, 0141; LA32-NEXT: ret142;143; LA64-LABEL: vavg_du:144; LA64: # %bb.0: # %entry145; LA64-NEXT: vld $vr0, $a1, 0146; LA64-NEXT: vld $vr1, $a2, 0147; LA64-NEXT: vavg.du $vr0, $vr0, $vr1148; LA64-NEXT: vst $vr0, $a0, 0149; LA64-NEXT: ret150entry:151 %va = load <2 x i64>, ptr %a152 %vb = load <2 x i64>, ptr %b153 %add = add <2 x i64> %va, %vb154 %shr = lshr <2 x i64> %add, <i64 1, i64 1>155 store <2 x i64> %shr, ptr %res156 ret void157}158 159define void @vavgr_b(ptr %res, ptr %a, ptr %b) nounwind {160; CHECK-LABEL: vavgr_b:161; CHECK: # %bb.0: # %entry162; CHECK-NEXT: vld $vr0, $a1, 0163; CHECK-NEXT: vld $vr1, $a2, 0164; CHECK-NEXT: vavgr.b $vr0, $vr0, $vr1165; CHECK-NEXT: vst $vr0, $a0, 0166; CHECK-NEXT: ret167entry:168 %va = load <16 x i8>, ptr %a169 %vb = load <16 x i8>, ptr %b170 %add = add <16 x i8> %va, %vb171 %add1 = add <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>172 %shr = ashr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>173 store <16 x i8> %shr, ptr %res174 ret void175}176 177define void @vavgr_h(ptr %res, ptr %a, ptr %b) nounwind {178; CHECK-LABEL: vavgr_h:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vld $vr0, $a1, 0181; CHECK-NEXT: vld $vr1, $a2, 0182; CHECK-NEXT: vavgr.h $vr0, $vr0, $vr1183; CHECK-NEXT: vst $vr0, $a0, 0184; CHECK-NEXT: ret185entry:186 %va = load <8 x i16>, ptr %a187 %vb = load <8 x i16>, ptr %b188 %add = add <8 x i16> %va, %vb189 %add1 = add <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>190 %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>191 store <8 x i16> %shr, ptr %res192 ret void193}194 195define void @vavgr_w(ptr %res, ptr %a, ptr %b) nounwind {196; CHECK-LABEL: vavgr_w:197; CHECK: # %bb.0: # %entry198; CHECK-NEXT: vld $vr0, $a1, 0199; CHECK-NEXT: vld $vr1, $a2, 0200; CHECK-NEXT: vavgr.w $vr0, $vr0, $vr1201; CHECK-NEXT: vst $vr0, $a0, 0202; CHECK-NEXT: ret203entry:204 %va = load <4 x i32>, ptr %a205 %vb = load <4 x i32>, ptr %b206 %add = add <4 x i32> %va, %vb207 %add1 = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>208 %shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>209 store <4 x i32> %shr, ptr %res210 ret void211}212 213define void @vavgr_d(ptr %res, ptr %a, ptr %b) nounwind {214; LA32-LABEL: vavgr_d:215; LA32: # %bb.0: # %entry216; LA32-NEXT: vld $vr0, $a1, 0217; LA32-NEXT: vld $vr1, $a2, 0218; LA32-NEXT: vadd.d $vr0, $vr0, $vr1219; LA32-NEXT: vaddi.du $vr0, $vr0, 1220; LA32-NEXT: vsrai.d $vr0, $vr0, 1221; LA32-NEXT: vst $vr0, $a0, 0222; LA32-NEXT: ret223;224; LA64-LABEL: vavgr_d:225; LA64: # %bb.0: # %entry226; LA64-NEXT: vld $vr0, $a1, 0227; LA64-NEXT: vld $vr1, $a2, 0228; LA64-NEXT: vavgr.d $vr0, $vr0, $vr1229; LA64-NEXT: vst $vr0, $a0, 0230; LA64-NEXT: ret231entry:232 %va = load <2 x i64>, ptr %a233 %vb = load <2 x i64>, ptr %b234 %add = add <2 x i64> %va, %vb235 %add1 = add <2 x i64> %add, <i64 1, i64 1>236 %shr = ashr <2 x i64> %add1, <i64 1, i64 1>237 store <2 x i64> %shr, ptr %res238 ret void239}240 241define void @vavgr_bu(ptr %res, ptr %a, ptr %b) nounwind {242; CHECK-LABEL: vavgr_bu:243; CHECK: # %bb.0: # %entry244; CHECK-NEXT: vld $vr0, $a1, 0245; CHECK-NEXT: vld $vr1, $a2, 0246; CHECK-NEXT: vavgr.bu $vr0, $vr0, $vr1247; CHECK-NEXT: vst $vr0, $a0, 0248; CHECK-NEXT: ret249entry:250 %va = load <16 x i8>, ptr %a251 %vb = load <16 x i8>, ptr %b252 %add = add <16 x i8> %va, %vb253 %add1 = add <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>254 %shr = lshr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>255 store <16 x i8> %shr, ptr %res256 ret void257}258 259define void @vavgr_hu(ptr %res, ptr %a, ptr %b) nounwind {260; CHECK-LABEL: vavgr_hu:261; CHECK: # %bb.0: # %entry262; CHECK-NEXT: vld $vr0, $a1, 0263; CHECK-NEXT: vld $vr1, $a2, 0264; CHECK-NEXT: vavgr.hu $vr0, $vr0, $vr1265; CHECK-NEXT: vst $vr0, $a0, 0266; CHECK-NEXT: ret267entry:268 %va = load <8 x i16>, ptr %a269 %vb = load <8 x i16>, ptr %b270 %add = add <8 x i16> %va, %vb271 %add1 = add <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>272 %shr = lshr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>273 store <8 x i16> %shr, ptr %res274 ret void275}276 277define void @vavgr_wu(ptr %res, ptr %a, ptr %b) nounwind {278; CHECK-LABEL: vavgr_wu:279; CHECK: # %bb.0: # %entry280; CHECK-NEXT: vld $vr0, $a1, 0281; CHECK-NEXT: vld $vr1, $a2, 0282; CHECK-NEXT: vavgr.wu $vr0, $vr0, $vr1283; CHECK-NEXT: vst $vr0, $a0, 0284; CHECK-NEXT: ret285entry:286 %va = load <4 x i32>, ptr %a287 %vb = load <4 x i32>, ptr %b288 %add = add <4 x i32> %va, %vb289 %add1 = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>290 %shr = lshr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>291 store <4 x i32> %shr, ptr %res292 ret void293}294 295define void @vavgr_du(ptr %res, ptr %a, ptr %b) nounwind {296; LA32-LABEL: vavgr_du:297; LA32: # %bb.0: # %entry298; LA32-NEXT: vld $vr0, $a1, 0299; LA32-NEXT: vld $vr1, $a2, 0300; LA32-NEXT: vadd.d $vr0, $vr0, $vr1301; LA32-NEXT: vaddi.du $vr0, $vr0, 1302; LA32-NEXT: vsrli.d $vr0, $vr0, 1303; LA32-NEXT: vst $vr0, $a0, 0304; LA32-NEXT: ret305;306; LA64-LABEL: vavgr_du:307; LA64: # %bb.0: # %entry308; LA64-NEXT: vld $vr0, $a1, 0309; LA64-NEXT: vld $vr1, $a2, 0310; LA64-NEXT: vavgr.du $vr0, $vr0, $vr1311; LA64-NEXT: vst $vr0, $a0, 0312; LA64-NEXT: ret313entry:314 %va = load <2 x i64>, ptr %a315 %vb = load <2 x i64>, ptr %b316 %add = add <2 x i64> %va, %vb317 %add1 = add <2 x i64> %add, <i64 1, i64 1>318 %shr = lshr <2 x i64> %add1, <i64 1, i64 1>319 store <2 x i64> %shr, ptr %res320 ret void321}322