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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5define void @fdiv_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {6; CHECK-LABEL: fdiv_v4f32:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vld $vr0, $a1, 09; CHECK-NEXT: vld $vr1, $a2, 010; CHECK-NEXT: vfdiv.s $vr0, $vr0, $vr111; CHECK-NEXT: vst $vr0, $a0, 012; CHECK-NEXT: ret13entry:14 %v0 = load <4 x float>, ptr %a015 %v1 = load <4 x float>, ptr %a116 %v2 = fdiv <4 x float> %v0, %v117 store <4 x float> %v2, ptr %res18 ret void19}20 21define void @fdiv_v2f64(ptr %res, ptr %a0, ptr %a1) nounwind {22; CHECK-LABEL: fdiv_v2f64:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vld $vr0, $a1, 025; CHECK-NEXT: vld $vr1, $a2, 026; CHECK-NEXT: vfdiv.d $vr0, $vr0, $vr127; CHECK-NEXT: vst $vr0, $a0, 028; CHECK-NEXT: ret29entry:30 %v0 = load <2 x double>, ptr %a031 %v1 = load <2 x double>, ptr %a132 %v2 = fdiv <2 x double> %v0, %v133 store <2 x double> %v2, ptr %res34 ret void35}36 37;; 1.0 / vec38define void @one_fdiv_v4f32(ptr %res, ptr %a0) nounwind {39; CHECK-LABEL: one_fdiv_v4f32:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vld $vr0, $a1, 042; CHECK-NEXT: vfrecip.s $vr0, $vr043; CHECK-NEXT: vst $vr0, $a0, 044; CHECK-NEXT: ret45entry:46 %v0 = load <4 x float>, ptr %a047 %div = fdiv <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %v048 store <4 x float> %div, ptr %res49 ret void50}51 52define void @one_fdiv_v2f64(ptr %res, ptr %a0) nounwind {53; LA32-LABEL: one_fdiv_v2f64:54; LA32: # %bb.0: # %entry55; LA32-NEXT: vld $vr0, $a1, 056; LA32-NEXT: vldi $vr1, -91257; LA32-NEXT: vfdiv.d $vr0, $vr1, $vr058; LA32-NEXT: vst $vr0, $a0, 059; LA32-NEXT: ret60;61; LA64-LABEL: one_fdiv_v2f64:62; LA64: # %bb.0: # %entry63; LA64-NEXT: vld $vr0, $a1, 064; LA64-NEXT: vfrecip.d $vr0, $vr065; LA64-NEXT: vst $vr0, $a0, 066; LA64-NEXT: ret67entry:68 %v0 = load <2 x double>, ptr %a069 %div = fdiv <2 x double> <double 1.0, double 1.0>, %v070 store <2 x double> %div, ptr %res71 ret void72}73