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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5define void @insert_16xi8(ptr %src, ptr %dst, i8 %ins) nounwind {6; CHECK-LABEL: insert_16xi8:7; CHECK: # %bb.0:8; CHECK-NEXT: vld $vr0, $a0, 09; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 110; CHECK-NEXT: vst $vr0, $a1, 011; CHECK-NEXT: ret12 %v = load volatile <16 x i8>, ptr %src13 %v_new = insertelement <16 x i8> %v, i8 %ins, i32 114 store <16 x i8> %v_new, ptr %dst15 ret void16}17 18define void @insert_8xi16(ptr %src, ptr %dst, i16 %ins) nounwind {19; CHECK-LABEL: insert_8xi16:20; CHECK: # %bb.0:21; CHECK-NEXT: vld $vr0, $a0, 022; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 123; CHECK-NEXT: vst $vr0, $a1, 024; CHECK-NEXT: ret25 %v = load volatile <8 x i16>, ptr %src26 %v_new = insertelement <8 x i16> %v, i16 %ins, i32 127 store <8 x i16> %v_new, ptr %dst28 ret void29}30 31define void @insert_4xi32(ptr %src, ptr %dst, i32 %ins) nounwind {32; CHECK-LABEL: insert_4xi32:33; CHECK: # %bb.0:34; CHECK-NEXT: vld $vr0, $a0, 035; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 136; CHECK-NEXT: vst $vr0, $a1, 037; CHECK-NEXT: ret38 %v = load volatile <4 x i32>, ptr %src39 %v_new = insertelement <4 x i32> %v, i32 %ins, i32 140 store <4 x i32> %v_new, ptr %dst41 ret void42}43 44define void @insert_2xi64(ptr %src, ptr %dst, i64 %ins) nounwind {45; LA32-LABEL: insert_2xi64:46; LA32: # %bb.0:47; LA32-NEXT: vld $vr0, $a0, 048; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 249; LA32-NEXT: vinsgr2vr.w $vr0, $a3, 350; LA32-NEXT: vst $vr0, $a1, 051; LA32-NEXT: ret52;53; LA64-LABEL: insert_2xi64:54; LA64: # %bb.0:55; LA64-NEXT: vld $vr0, $a0, 056; LA64-NEXT: vinsgr2vr.d $vr0, $a2, 157; LA64-NEXT: vst $vr0, $a1, 058; LA64-NEXT: ret59 %v = load volatile <2 x i64>, ptr %src60 %v_new = insertelement <2 x i64> %v, i64 %ins, i32 161 store <2 x i64> %v_new, ptr %dst62 ret void63}64 65define void @insert_4xfloat(ptr %src, ptr %dst, float %ins) nounwind {66; CHECK-LABEL: insert_4xfloat:67; CHECK: # %bb.0:68; CHECK-NEXT: vld $vr1, $a0, 069; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr070; CHECK-NEXT: vextrins.w $vr1, $vr0, 1671; CHECK-NEXT: vst $vr1, $a1, 072; CHECK-NEXT: ret73 %v = load volatile <4 x float>, ptr %src74 %v_new = insertelement <4 x float> %v, float %ins, i32 175 store <4 x float> %v_new, ptr %dst76 ret void77}78 79define void @insert_2xdouble(ptr %src, ptr %dst, double %ins) nounwind {80; CHECK-LABEL: insert_2xdouble:81; CHECK: # %bb.0:82; CHECK-NEXT: vld $vr1, $a0, 083; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr084; CHECK-NEXT: vextrins.d $vr1, $vr0, 1685; CHECK-NEXT: vst $vr1, $a1, 086; CHECK-NEXT: ret87 %v = load volatile <2 x double>, ptr %src88 %v_new = insertelement <2 x double> %v, double %ins, i32 189 store <2 x double> %v_new, ptr %dst90 ret void91}92 93define void @insert_16xi8_idx(ptr %src, ptr %dst, i8 %ins, i32 %idx) nounwind {94; LA32-LABEL: insert_16xi8_idx:95; LA32: # %bb.0:96; LA32-NEXT: pcalau12i $a4, %pc_hi20(.LCPI6_0)97; LA32-NEXT: vld $vr0, $a4, %pc_lo12(.LCPI6_0)98; LA32-NEXT: vld $vr1, $a0, 099; LA32-NEXT: vreplgr2vr.b $vr2, $a3100; LA32-NEXT: vseq.b $vr0, $vr2, $vr0101; LA32-NEXT: vreplgr2vr.b $vr2, $a2102; LA32-NEXT: vbitsel.v $vr0, $vr1, $vr2, $vr0103; LA32-NEXT: vst $vr0, $a1, 0104; LA32-NEXT: ret105;106; LA64-LABEL: insert_16xi8_idx:107; LA64: # %bb.0:108; LA64-NEXT: pcalau12i $a4, %pc_hi20(.LCPI6_0)109; LA64-NEXT: vld $vr0, $a4, %pc_lo12(.LCPI6_0)110; LA64-NEXT: vld $vr1, $a0, 0111; LA64-NEXT: bstrpick.d $a0, $a3, 31, 0112; LA64-NEXT: vreplgr2vr.b $vr2, $a0113; LA64-NEXT: vseq.b $vr0, $vr2, $vr0114; LA64-NEXT: vreplgr2vr.b $vr2, $a2115; LA64-NEXT: vbitsel.v $vr0, $vr1, $vr2, $vr0116; LA64-NEXT: vst $vr0, $a1, 0117; LA64-NEXT: ret118 %v = load volatile <16 x i8>, ptr %src119 %v_new = insertelement <16 x i8> %v, i8 %ins, i32 %idx120 store <16 x i8> %v_new, ptr %dst121 ret void122}123 124define void @insert_8xi16_idx(ptr %src, ptr %dst, i16 %ins, i32 %idx) nounwind {125; LA32-LABEL: insert_8xi16_idx:126; LA32: # %bb.0:127; LA32-NEXT: pcalau12i $a4, %pc_hi20(.LCPI7_0)128; LA32-NEXT: vld $vr0, $a4, %pc_lo12(.LCPI7_0)129; LA32-NEXT: vld $vr1, $a0, 0130; LA32-NEXT: vreplgr2vr.h $vr2, $a3131; LA32-NEXT: vseq.h $vr0, $vr2, $vr0132; LA32-NEXT: vreplgr2vr.h $vr2, $a2133; LA32-NEXT: vbitsel.v $vr0, $vr1, $vr2, $vr0134; LA32-NEXT: vst $vr0, $a1, 0135; LA32-NEXT: ret136;137; LA64-LABEL: insert_8xi16_idx:138; LA64: # %bb.0:139; LA64-NEXT: pcalau12i $a4, %pc_hi20(.LCPI7_0)140; LA64-NEXT: vld $vr0, $a4, %pc_lo12(.LCPI7_0)141; LA64-NEXT: vld $vr1, $a0, 0142; LA64-NEXT: bstrpick.d $a0, $a3, 31, 0143; LA64-NEXT: vreplgr2vr.h $vr2, $a0144; LA64-NEXT: vseq.h $vr0, $vr2, $vr0145; LA64-NEXT: vreplgr2vr.h $vr2, $a2146; LA64-NEXT: vbitsel.v $vr0, $vr1, $vr2, $vr0147; LA64-NEXT: vst $vr0, $a1, 0148; LA64-NEXT: ret149 %v = load volatile <8 x i16>, ptr %src150 %v_new = insertelement <8 x i16> %v, i16 %ins, i32 %idx151 store <8 x i16> %v_new, ptr %dst152 ret void153}154 155define void @insert_4xi32_idx(ptr %src, ptr %dst, i32 %ins, i32 %idx) nounwind {156; LA32-LABEL: insert_4xi32_idx:157; LA32: # %bb.0:158; LA32-NEXT: pcalau12i $a4, %pc_hi20(.LCPI8_0)159; LA32-NEXT: vld $vr0, $a4, %pc_lo12(.LCPI8_0)160; LA32-NEXT: vld $vr1, $a0, 0161; LA32-NEXT: vreplgr2vr.w $vr2, $a3162; LA32-NEXT: vseq.w $vr0, $vr2, $vr0163; LA32-NEXT: vreplgr2vr.w $vr2, $a2164; LA32-NEXT: vbitsel.v $vr0, $vr1, $vr2, $vr0165; LA32-NEXT: vst $vr0, $a1, 0166; LA32-NEXT: ret167;168; LA64-LABEL: insert_4xi32_idx:169; LA64: # %bb.0:170; LA64-NEXT: pcalau12i $a4, %pc_hi20(.LCPI8_0)171; LA64-NEXT: vld $vr0, $a4, %pc_lo12(.LCPI8_0)172; LA64-NEXT: vld $vr1, $a0, 0173; LA64-NEXT: bstrpick.d $a0, $a3, 31, 0174; LA64-NEXT: vreplgr2vr.w $vr2, $a0175; LA64-NEXT: vseq.w $vr0, $vr2, $vr0176; LA64-NEXT: vreplgr2vr.w $vr2, $a2177; LA64-NEXT: vbitsel.v $vr0, $vr1, $vr2, $vr0178; LA64-NEXT: vst $vr0, $a1, 0179; LA64-NEXT: ret180 %v = load volatile <4 x i32>, ptr %src181 %v_new = insertelement <4 x i32> %v, i32 %ins, i32 %idx182 store <4 x i32> %v_new, ptr %dst183 ret void184}185 186define void @insert_2xi64_idx(ptr %src, ptr %dst, i64 %ins, i32 %idx) nounwind {187; LA32-LABEL: insert_2xi64_idx:188; LA32: # %bb.0:189; LA32-NEXT: pcalau12i $a5, %pc_hi20(.LCPI9_0)190; LA32-NEXT: vld $vr0, $a5, %pc_lo12(.LCPI9_0)191; LA32-NEXT: add.w $a4, $a4, $a4192; LA32-NEXT: vld $vr1, $a0, 0193; LA32-NEXT: vreplgr2vr.w $vr2, $a4194; LA32-NEXT: vseq.w $vr2, $vr2, $vr0195; LA32-NEXT: vreplgr2vr.w $vr3, $a2196; LA32-NEXT: vbitsel.v $vr1, $vr1, $vr3, $vr2197; LA32-NEXT: addi.w $a0, $a4, 1198; LA32-NEXT: vreplgr2vr.w $vr2, $a0199; LA32-NEXT: vseq.w $vr0, $vr2, $vr0200; LA32-NEXT: vreplgr2vr.w $vr2, $a3201; LA32-NEXT: vbitsel.v $vr0, $vr1, $vr2, $vr0202; LA32-NEXT: vst $vr0, $a1, 0203; LA32-NEXT: ret204;205; LA64-LABEL: insert_2xi64_idx:206; LA64: # %bb.0:207; LA64-NEXT: pcalau12i $a4, %pc_hi20(.LCPI9_0)208; LA64-NEXT: vld $vr0, $a4, %pc_lo12(.LCPI9_0)209; LA64-NEXT: vld $vr1, $a0, 0210; LA64-NEXT: bstrpick.d $a0, $a3, 31, 0211; LA64-NEXT: vreplgr2vr.d $vr2, $a0212; LA64-NEXT: vseq.d $vr0, $vr2, $vr0213; LA64-NEXT: vreplgr2vr.d $vr2, $a2214; LA64-NEXT: vbitsel.v $vr0, $vr1, $vr2, $vr0215; LA64-NEXT: vst $vr0, $a1, 0216; LA64-NEXT: ret217 %v = load volatile <2 x i64>, ptr %src218 %v_new = insertelement <2 x i64> %v, i64 %ins, i32 %idx219 store <2 x i64> %v_new, ptr %dst220 ret void221}222 223define void @insert_4xfloat_idx(ptr %src, ptr %dst, float %ins, i32 %idx) nounwind {224; LA32-LABEL: insert_4xfloat_idx:225; LA32: # %bb.0:226; LA32-NEXT: pcalau12i $a3, %pc_hi20(.LCPI10_0)227; LA32-NEXT: vld $vr1, $a3, %pc_lo12(.LCPI10_0)228; LA32-NEXT: # kill: def $f0 killed $f0 def $vr0229; LA32-NEXT: vld $vr2, $a0, 0230; LA32-NEXT: vreplgr2vr.w $vr3, $a2231; LA32-NEXT: vseq.w $vr1, $vr3, $vr1232; LA32-NEXT: vreplvei.w $vr0, $vr0, 0233; LA32-NEXT: vbitsel.v $vr0, $vr2, $vr0, $vr1234; LA32-NEXT: vst $vr0, $a1, 0235; LA32-NEXT: ret236;237; LA64-LABEL: insert_4xfloat_idx:238; LA64: # %bb.0:239; LA64-NEXT: # kill: def $f0 killed $f0 def $vr0240; LA64-NEXT: pcalau12i $a3, %pc_hi20(.LCPI10_0)241; LA64-NEXT: vld $vr1, $a3, %pc_lo12(.LCPI10_0)242; LA64-NEXT: vld $vr2, $a0, 0243; LA64-NEXT: bstrpick.d $a0, $a2, 31, 0244; LA64-NEXT: vreplgr2vr.w $vr3, $a0245; LA64-NEXT: vseq.w $vr1, $vr3, $vr1246; LA64-NEXT: vreplvei.w $vr0, $vr0, 0247; LA64-NEXT: vbitsel.v $vr0, $vr2, $vr0, $vr1248; LA64-NEXT: vst $vr0, $a1, 0249; LA64-NEXT: ret250 %v = load volatile <4 x float>, ptr %src251 %v_new = insertelement <4 x float> %v, float %ins, i32 %idx252 store <4 x float> %v_new, ptr %dst253 ret void254}255 256define void @insert_2xdouble_idx(ptr %src, ptr %dst, double %ins, i32 %idx) nounwind {257; LA32-LABEL: insert_2xdouble_idx:258; LA32: # %bb.0:259; LA32-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0260; LA32-NEXT: vld $vr1, $a0, 0261; LA32-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)262; LA32-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI11_0)263; LA32-NEXT: vrepli.b $vr3, 0264; LA32-NEXT: vinsgr2vr.w $vr3, $a2, 0265; LA32-NEXT: vinsgr2vr.w $vr3, $a2, 2266; LA32-NEXT: vseq.d $vr2, $vr3, $vr2267; LA32-NEXT: vreplvei.d $vr0, $vr0, 0268; LA32-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2269; LA32-NEXT: vst $vr0, $a1, 0270; LA32-NEXT: ret271;272; LA64-LABEL: insert_2xdouble_idx:273; LA64: # %bb.0:274; LA64-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0275; LA64-NEXT: pcalau12i $a3, %pc_hi20(.LCPI11_0)276; LA64-NEXT: vld $vr1, $a3, %pc_lo12(.LCPI11_0)277; LA64-NEXT: vld $vr2, $a0, 0278; LA64-NEXT: bstrpick.d $a0, $a2, 31, 0279; LA64-NEXT: vreplgr2vr.d $vr3, $a0280; LA64-NEXT: vseq.d $vr1, $vr3, $vr1281; LA64-NEXT: vreplvei.d $vr0, $vr0, 0282; LA64-NEXT: vbitsel.v $vr0, $vr2, $vr0, $vr1283; LA64-NEXT: vst $vr0, $a1, 0284; LA64-NEXT: ret285 %v = load volatile <2 x double>, ptr %src286 %v_new = insertelement <2 x double> %v, double %ins, i32 %idx287 store <2 x double> %v_new, ptr %dst288 ret void289}290