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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5define void @nor_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {6; CHECK-LABEL: nor_v16i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vld $vr0, $a1, 09; CHECK-NEXT: vld $vr1, $a2, 010; CHECK-NEXT: vnor.v $vr0, $vr0, $vr111; CHECK-NEXT: vst $vr0, $a0, 012; CHECK-NEXT: ret13entry:14 %v0 = load <16 x i8>, ptr %a015 %v1 = load <16 x i8>, ptr %a116 %v2 = or <16 x i8> %v0, %v117 %v3 = xor <16 x i8> %v2, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>18 store <16 x i8> %v3, ptr %res19 ret void20}21 22define void @nor_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {23; CHECK-LABEL: nor_v8i16:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vld $vr0, $a1, 026; CHECK-NEXT: vld $vr1, $a2, 027; CHECK-NEXT: vnor.v $vr0, $vr0, $vr128; CHECK-NEXT: vst $vr0, $a0, 029; CHECK-NEXT: ret30entry:31 %v0 = load <8 x i16>, ptr %a032 %v1 = load <8 x i16>, ptr %a133 %v2 = or <8 x i16> %v0, %v134 %v3 = xor <8 x i16> %v2, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>35 store <8 x i16> %v3, ptr %res36 ret void37}38 39define void @nor_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {40; CHECK-LABEL: nor_v4i32:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vld $vr0, $a1, 043; CHECK-NEXT: vld $vr1, $a2, 044; CHECK-NEXT: vnor.v $vr0, $vr0, $vr145; CHECK-NEXT: vst $vr0, $a0, 046; CHECK-NEXT: ret47entry:48 %v0 = load <4 x i32>, ptr %a049 %v1 = load <4 x i32>, ptr %a150 %v2 = or <4 x i32> %v0, %v151 %v3 = xor <4 x i32> %v2, <i32 -1, i32 -1, i32 -1, i32 -1>52 store <4 x i32> %v3, ptr %res53 ret void54}55 56define void @nor_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {57; CHECK-LABEL: nor_v2i64:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vld $vr0, $a1, 060; CHECK-NEXT: vld $vr1, $a2, 061; CHECK-NEXT: vnor.v $vr0, $vr0, $vr162; CHECK-NEXT: vst $vr0, $a0, 063; CHECK-NEXT: ret64entry:65 %v0 = load <2 x i64>, ptr %a066 %v1 = load <2 x i64>, ptr %a167 %v2 = or <2 x i64> %v0, %v168 %v3 = xor <2 x i64> %v2, <i64 -1, i64 -1>69 store <2 x i64> %v3, ptr %res70 ret void71}72 73define void @nor_u_v16i8(ptr %res, ptr %a0) nounwind {74; CHECK-LABEL: nor_u_v16i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vld $vr0, $a1, 077; CHECK-NEXT: vnori.b $vr0, $vr0, 3178; CHECK-NEXT: vst $vr0, $a0, 079; CHECK-NEXT: ret80entry:81 %v0 = load <16 x i8>, ptr %a082 %v1 = or <16 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>83 %v2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>84 store <16 x i8> %v2, ptr %res85 ret void86}87 88define void @nor_u_v8i16(ptr %res, ptr %a0) nounwind {89; CHECK-LABEL: nor_u_v8i16:90; CHECK: # %bb.0: # %entry91; CHECK-NEXT: vld $vr0, $a1, 092; CHECK-NEXT: vrepli.h $vr1, 3193; CHECK-NEXT: vnor.v $vr0, $vr0, $vr194; CHECK-NEXT: vst $vr0, $a0, 095; CHECK-NEXT: ret96entry:97 %v0 = load <8 x i16>, ptr %a098 %v1 = or <8 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>99 %v2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>100 store <8 x i16> %v2, ptr %res101 ret void102}103 104define void @nor_u_v4i32(ptr %res, ptr %a0) nounwind {105; CHECK-LABEL: nor_u_v4i32:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: vld $vr0, $a1, 0108; CHECK-NEXT: vrepli.w $vr1, 31109; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1110; CHECK-NEXT: vst $vr0, $a0, 0111; CHECK-NEXT: ret112entry:113 %v0 = load <4 x i32>, ptr %a0114 %v1 = or <4 x i32> %v0, <i32 31, i32 31, i32 31, i32 31>115 %v2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>116 store <4 x i32> %v2, ptr %res117 ret void118}119 120define void @nor_u_v2i64(ptr %res, ptr %a0) nounwind {121; CHECK-LABEL: nor_u_v2i64:122; CHECK: # %bb.0: # %entry123; CHECK-NEXT: vld $vr0, $a1, 0124; CHECK-NEXT: vrepli.d $vr1, 31125; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1126; CHECK-NEXT: vst $vr0, $a0, 0127; CHECK-NEXT: ret128entry:129 %v0 = load <2 x i64>, ptr %a0130 %v1 = or <2 x i64> %v0, <i64 31, i64 31>131 %v2 = xor <2 x i64> %v1, <i64 -1, i64 -1>132 store <2 x i64> %v2, ptr %res133 ret void134}135