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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5define void @sdiv_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {6; CHECK-LABEL: sdiv_v16i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vld $vr0, $a1, 09; CHECK-NEXT: vld $vr1, $a2, 010; CHECK-NEXT: vdiv.b $vr0, $vr0, $vr111; CHECK-NEXT: vst $vr0, $a0, 012; CHECK-NEXT: ret13entry:14 %v0 = load <16 x i8>, ptr %a015 %v1 = load <16 x i8>, ptr %a116 %v2 = sdiv <16 x i8> %v0, %v117 store <16 x i8> %v2, ptr %res18 ret void19}20 21define void @sdiv_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {22; CHECK-LABEL: sdiv_v8i16:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vld $vr0, $a1, 025; CHECK-NEXT: vld $vr1, $a2, 026; CHECK-NEXT: vdiv.h $vr0, $vr0, $vr127; CHECK-NEXT: vst $vr0, $a0, 028; CHECK-NEXT: ret29entry:30 %v0 = load <8 x i16>, ptr %a031 %v1 = load <8 x i16>, ptr %a132 %v2 = sdiv <8 x i16> %v0, %v133 store <8 x i16> %v2, ptr %res34 ret void35}36 37define void @sdiv_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {38; CHECK-LABEL: sdiv_v4i32:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vld $vr0, $a1, 041; CHECK-NEXT: vld $vr1, $a2, 042; CHECK-NEXT: vdiv.w $vr0, $vr0, $vr143; CHECK-NEXT: vst $vr0, $a0, 044; CHECK-NEXT: ret45entry:46 %v0 = load <4 x i32>, ptr %a047 %v1 = load <4 x i32>, ptr %a148 %v2 = sdiv <4 x i32> %v0, %v149 store <4 x i32> %v2, ptr %res50 ret void51}52 53define void @sdiv_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {54; CHECK-LABEL: sdiv_v2i64:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vld $vr0, $a1, 057; CHECK-NEXT: vld $vr1, $a2, 058; CHECK-NEXT: vdiv.d $vr0, $vr0, $vr159; CHECK-NEXT: vst $vr0, $a0, 060; CHECK-NEXT: ret61entry:62 %v0 = load <2 x i64>, ptr %a063 %v1 = load <2 x i64>, ptr %a164 %v2 = sdiv <2 x i64> %v0, %v165 store <2 x i64> %v2, ptr %res66 ret void67}68 69define void @sdiv_v16i8_8(ptr %res, ptr %a0) nounwind {70; CHECK-LABEL: sdiv_v16i8_8:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vld $vr0, $a1, 073; CHECK-NEXT: vsrai.b $vr1, $vr0, 774; CHECK-NEXT: vsrli.b $vr1, $vr1, 575; CHECK-NEXT: vadd.b $vr0, $vr0, $vr176; CHECK-NEXT: vsrai.b $vr0, $vr0, 377; CHECK-NEXT: vst $vr0, $a0, 078; CHECK-NEXT: ret79entry:80 %v0 = load <16 x i8>, ptr %a081 %v1 = sdiv <16 x i8> %v0, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>82 store <16 x i8> %v1, ptr %res83 ret void84}85 86define void @sdiv_v8i16_8(ptr %res, ptr %a0) nounwind {87; CHECK-LABEL: sdiv_v8i16_8:88; CHECK: # %bb.0: # %entry89; CHECK-NEXT: vld $vr0, $a1, 090; CHECK-NEXT: vsrai.h $vr1, $vr0, 1591; CHECK-NEXT: vsrli.h $vr1, $vr1, 1392; CHECK-NEXT: vadd.h $vr0, $vr0, $vr193; CHECK-NEXT: vsrai.h $vr0, $vr0, 394; CHECK-NEXT: vst $vr0, $a0, 095; CHECK-NEXT: ret96entry:97 %v0 = load <8 x i16>, ptr %a098 %v1 = sdiv <8 x i16> %v0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>99 store <8 x i16> %v1, ptr %res100 ret void101}102 103define void @sdiv_v4i32_8(ptr %res, ptr %a0) nounwind {104; CHECK-LABEL: sdiv_v4i32_8:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vld $vr0, $a1, 0107; CHECK-NEXT: vsrai.w $vr1, $vr0, 31108; CHECK-NEXT: vsrli.w $vr1, $vr1, 29109; CHECK-NEXT: vadd.w $vr0, $vr0, $vr1110; CHECK-NEXT: vsrai.w $vr0, $vr0, 3111; CHECK-NEXT: vst $vr0, $a0, 0112; CHECK-NEXT: ret113entry:114 %v0 = load <4 x i32>, ptr %a0115 %v1 = sdiv <4 x i32> %v0, <i32 8, i32 8, i32 8, i32 8>116 store <4 x i32> %v1, ptr %res117 ret void118}119 120define void @sdiv_v2i64_8(ptr %res, ptr %a0) nounwind {121; CHECK-LABEL: sdiv_v2i64_8:122; CHECK: # %bb.0: # %entry123; CHECK-NEXT: vld $vr0, $a1, 0124; CHECK-NEXT: vsrai.d $vr1, $vr0, 63125; CHECK-NEXT: vsrli.d $vr1, $vr1, 61126; CHECK-NEXT: vadd.d $vr0, $vr0, $vr1127; CHECK-NEXT: vsrai.d $vr0, $vr0, 3128; CHECK-NEXT: vst $vr0, $a0, 0129; CHECK-NEXT: ret130entry:131 %v0 = load <2 x i64>, ptr %a0132 %v1 = sdiv <2 x i64> %v0, <i64 8, i64 8>133 store <2 x i64> %v1, ptr %res134 ret void135}136