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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s4 5;; vilvl.b6define <16 x i8> @shufflevector_vilvl_v16i8(<16 x i8> %a, <16 x i8> %b) {7; CHECK-LABEL: shufflevector_vilvl_v16i8:8; CHECK: # %bb.0:9; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr010; CHECK-NEXT: ret11 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>12 ret <16 x i8> %c13}14 15;; vilvl.h16define <8 x i16> @shufflevector_vilvl_v8i16(<8 x i16> %a, <8 x i16> %b) {17; CHECK-LABEL: shufflevector_vilvl_v8i16:18; CHECK: # %bb.0:19; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr020; CHECK-NEXT: ret21 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>22 ret <8 x i16> %c23}24 25;; vilvl.w26define <4 x i32> @shufflevector_vilvl_v4i32(<4 x i32> %a, <4 x i32> %b) {27; CHECK-LABEL: shufflevector_vilvl_v4i32:28; CHECK: # %bb.0:29; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr030; CHECK-NEXT: ret31 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>32 ret <4 x i32> %c33}34 35;; vilvl.w36define <4 x float> @shufflevector_vilvl_v4f32(<4 x float> %a, <4 x float> %b) {37; CHECK-LABEL: shufflevector_vilvl_v4f32:38; CHECK: # %bb.0:39; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr040; CHECK-NEXT: ret41 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>42 ret <4 x float> %c43}44 45;; vilvh.b46define <16 x i8> @shufflevector_vilvh_v16i8(<16 x i8> %a, <16 x i8> %b) {47; CHECK-LABEL: shufflevector_vilvh_v16i8:48; CHECK: # %bb.0:49; CHECK-NEXT: vilvh.b $vr0, $vr1, $vr050; CHECK-NEXT: ret51 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>52 ret <16 x i8> %c53}54 55;; vilvh.h56define <8 x i16> @shufflevector_vilvh_v8i16(<8 x i16> %a, <8 x i16> %b) {57; CHECK-LABEL: shufflevector_vilvh_v8i16:58; CHECK: # %bb.0:59; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr060; CHECK-NEXT: ret61 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>62 ret <8 x i16> %c63}64 65;; vilvh.w66define <4 x i32> @shufflevector_vilvh_v4i32(<4 x i32> %a, <4 x i32> %b) {67; CHECK-LABEL: shufflevector_vilvh_v4i32:68; CHECK: # %bb.0:69; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr070; CHECK-NEXT: ret71 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7>72 ret <4 x i32> %c73}74 75;; vilvh.w76define <4 x float> @shufflevector_vilvh_v4f32(<4 x float> %a, <4 x float> %b) {77; CHECK-LABEL: shufflevector_vilvh_v4f32:78; CHECK: # %bb.0:79; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr080; CHECK-NEXT: ret81 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7>82 ret <4 x float> %c83}84