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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s4 5;; vpackev.b6define <16 x i8> @shufflevector_pack_ev_v16i8(<16 x i8> %a, <16 x i8> %b) {7; CHECK-LABEL: shufflevector_pack_ev_v16i8:8; CHECK: # %bb.0:9; CHECK-NEXT: vpackev.b $vr0, $vr1, $vr010; CHECK-NEXT: ret11 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>12 ret <16 x i8> %c13}14 15;; vpackev.h16define <8 x i16> @shufflevector_pack_ev_v8i16(<8 x i16> %a, <8 x i16> %b) {17; CHECK-LABEL: shufflevector_pack_ev_v8i16:18; CHECK: # %bb.0:19; CHECK-NEXT: vpackev.h $vr0, $vr1, $vr020; CHECK-NEXT: ret21 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>22 ret <8 x i16> %c23}24 25;; vpackev.w26define <4 x i32> @shufflevector_pack_ev_v4i32(<4 x i32> %a, <4 x i32> %b) {27; CHECK-LABEL: shufflevector_pack_ev_v4i32:28; CHECK: # %bb.0:29; CHECK-NEXT: vpackev.w $vr0, $vr1, $vr030; CHECK-NEXT: ret31 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>32 ret <4 x i32> %c33}34 35;; vpickev.d/vpackev.d/vilvl.d36define <2 x i64> @shufflevector_pack_ev_v2i64(<2 x i64> %a, <2 x i64> %b) {37; CHECK-LABEL: shufflevector_pack_ev_v2i64:38; CHECK: # %bb.0:39; CHECK-NEXT: vpackev.d $vr0, $vr1, $vr040; CHECK-NEXT: ret41 %c = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>42 ret <2 x i64> %c43}44 45;; vpackev.w46define <4 x float> @shufflevector_pack_ev_v4f32(<4 x float> %a, <4 x float> %b) {47; CHECK-LABEL: shufflevector_pack_ev_v4f32:48; CHECK: # %bb.0:49; CHECK-NEXT: vpackev.w $vr0, $vr1, $vr050; CHECK-NEXT: ret51 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>52 ret <4 x float> %c53}54 55;; vpickev.d/vpackev.d/vilvl.d56define <2 x double> @shufflevector_pack_ev_v2f64(<2 x double> %a, <2 x double> %b) {57; CHECK-LABEL: shufflevector_pack_ev_v2f64:58; CHECK: # %bb.0:59; CHECK-NEXT: vpackev.d $vr0, $vr1, $vr060; CHECK-NEXT: ret61 %c = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>62 ret <2 x double> %c63}64 65;; vpackod.b66define <16 x i8> @shufflevector_pack_od_v16i8(<16 x i8> %a, <16 x i8> %b) {67; CHECK-LABEL: shufflevector_pack_od_v16i8:68; CHECK: # %bb.0:69; CHECK-NEXT: vpackod.b $vr0, $vr1, $vr070; CHECK-NEXT: ret71 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>72 ret <16 x i8> %c73}74 75;; vpackod.h76define <8 x i16> @shufflevector_pack_od_v8i16(<8 x i16> %a, <8 x i16> %b) {77; CHECK-LABEL: shufflevector_pack_od_v8i16:78; CHECK: # %bb.0:79; CHECK-NEXT: vpackod.h $vr0, $vr1, $vr080; CHECK-NEXT: ret81 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>82 ret <8 x i16> %c83}84 85;; vpackod.w86define <4 x i32> @shufflevector_pack_od_v4i32(<4 x i32> %a, <4 x i32> %b) {87; CHECK-LABEL: shufflevector_pack_od_v4i32:88; CHECK: # %bb.0:89; CHECK-NEXT: vpackod.w $vr0, $vr1, $vr090; CHECK-NEXT: ret91 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>92 ret <4 x i32> %c93}94 95;; vpickod.d/vpackod.d/vilvh.d96define <2 x i64> @shufflodector_pack_od_v2i64(<2 x i64> %a, <2 x i64> %b) {97; CHECK-LABEL: shufflodector_pack_od_v2i64:98; CHECK: # %bb.0:99; CHECK-NEXT: vpackod.d $vr0, $vr1, $vr0100; CHECK-NEXT: ret101 %c = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>102 ret <2 x i64> %c103}104 105;; vpackod.w106define <4 x float> @shufflodector_pack_od_v4f32(<4 x float> %a, <4 x float> %b) {107; CHECK-LABEL: shufflodector_pack_od_v4f32:108; CHECK: # %bb.0:109; CHECK-NEXT: vpackod.w $vr0, $vr1, $vr0110; CHECK-NEXT: ret111 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>112 ret <4 x float> %c113}114 115;; vpickod.d/vpackod.d/vilvh.d116define <2 x double> @shufflodector_pack_od_v2f64(<2 x double> %a, <2 x double> %b) {117; CHECK-LABEL: shufflodector_pack_od_v2f64:118; CHECK: # %bb.0:119; CHECK-NEXT: vpackod.d $vr0, $vr1, $vr0120; CHECK-NEXT: ret121 %c = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>122 ret <2 x double> %c123}124