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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx %s -o - | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s4 5define <16 x i8> @shufflevector_v16i8(<16 x i8> %a, <16 x i8> %b) {6; CHECK-LABEL: shufflevector_v16i8:7; CHECK: # %bb.0:8; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)9; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI0_0)10; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr211; CHECK-NEXT: ret12 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 8, i32 10, i32 12, i32 15, i32 2, i32 4, i32 6, i32 8, i32 25, i32 30, i32 31, i32 31>13 ret <16 x i8> %c14}15 16;; vshuf.h17define <8 x i16> @shufflevector_v8i16(<8 x i16> %a, <8 x i16> %b) {18; CHECK-LABEL: shufflevector_v8i16:19; CHECK: # %bb.0:20; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)21; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI1_0)22; CHECK-NEXT: vshuf.h $vr2, $vr1, $vr023; CHECK-NEXT: vori.b $vr0, $vr2, 024; CHECK-NEXT: ret25 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 8, i32 10, i32 12, i32 15>26 ret <8 x i16> %c27}28 29;; vshuf.w30define <4 x i32> @shufflevector_v4i32(<4 x i32> %a, <4 x i32> %b) {31; CHECK-LABEL: shufflevector_v4i32:32; CHECK: # %bb.0:33; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)34; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI2_0)35; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr036; CHECK-NEXT: vori.b $vr0, $vr2, 037; CHECK-NEXT: ret38 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 3, i32 5, i32 7>39 ret <4 x i32> %c40}41 42;; vshuf.d43define <2 x i64> @shufflevector_v2i64(<2 x i64> %a, <2 x i64> %b) {44; CHECK-LABEL: shufflevector_v2i64:45; CHECK: # %bb.0:46; CHECK-NEXT: vshuf4i.d $vr0, $vr1, 1247; CHECK-NEXT: ret48 %c = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 3>49 ret <2 x i64> %c50}51 52;; vshuf.w53define <4 x float> @shufflevector_v4f32(<4 x float> %a, <4 x float> %b) {54; CHECK-LABEL: shufflevector_v4f32:55; CHECK: # %bb.0:56; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)57; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI4_0)58; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr059; CHECK-NEXT: vori.b $vr0, $vr2, 060; CHECK-NEXT: ret61 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 3, i32 5, i32 7>62 ret <4 x float> %c63}64 65;; vshuf.d66define <2 x double> @shufflevector_v2f64(<2 x double> %a, <2 x double> %b) {67; CHECK-LABEL: shufflevector_v2f64:68; CHECK: # %bb.0:69; CHECK-NEXT: vshuf4i.d $vr0, $vr1, 1270; CHECK-NEXT: ret71 %c = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 3>72 ret <2 x double> %c73}74