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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc -mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s4 5define <16 x i8> @vssub_b(<16 x i8> %a, <16 x i8> %b) {6; CHECK-LABEL: vssub_b:7; CHECK: # %bb.0:8; CHECK-NEXT: vssub.b $vr0, $vr0, $vr19; CHECK-NEXT: ret10 %ret = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %a, <16 x i8> %b)11 ret <16 x i8> %ret12}13 14define <8 x i16> @vssub_h(<8 x i16> %a, <8 x i16> %b) {15; CHECK-LABEL: vssub_h:16; CHECK: # %bb.0:17; CHECK-NEXT: vssub.h $vr0, $vr0, $vr118; CHECK-NEXT: ret19 %ret = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a, <8 x i16> %b)20 ret <8 x i16> %ret21}22 23define <4 x i32> @vssub_w(<4 x i32> %a, <4 x i32> %b) {24; CHECK-LABEL: vssub_w:25; CHECK: # %bb.0:26; CHECK-NEXT: vssub.w $vr0, $vr0, $vr127; CHECK-NEXT: ret28 %ret = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)29 ret <4 x i32> %ret30}31 32define <2 x i64> @vssub_d(<2 x i64> %a, <2 x i64> %b) {33; CHECK-LABEL: vssub_d:34; CHECK: # %bb.0:35; CHECK-NEXT: vssub.d $vr0, $vr0, $vr136; CHECK-NEXT: ret37 %ret = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %a, <2 x i64> %b)38 ret <2 x i64> %ret39}40 41declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)42declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)43declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)44declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>)45