124 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5define void @udiv_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {6; CHECK-LABEL: udiv_v16i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vld $vr0, $a1, 09; CHECK-NEXT: vld $vr1, $a2, 010; CHECK-NEXT: vdiv.bu $vr0, $vr0, $vr111; CHECK-NEXT: vst $vr0, $a0, 012; CHECK-NEXT: ret13entry:14 %v0 = load <16 x i8>, ptr %a015 %v1 = load <16 x i8>, ptr %a116 %v2 = udiv <16 x i8> %v0, %v117 store <16 x i8> %v2, ptr %res18 ret void19}20 21define void @udiv_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {22; CHECK-LABEL: udiv_v8i16:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vld $vr0, $a1, 025; CHECK-NEXT: vld $vr1, $a2, 026; CHECK-NEXT: vdiv.hu $vr0, $vr0, $vr127; CHECK-NEXT: vst $vr0, $a0, 028; CHECK-NEXT: ret29entry:30 %v0 = load <8 x i16>, ptr %a031 %v1 = load <8 x i16>, ptr %a132 %v2 = udiv <8 x i16> %v0, %v133 store <8 x i16> %v2, ptr %res34 ret void35}36 37define void @udiv_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {38; CHECK-LABEL: udiv_v4i32:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vld $vr0, $a1, 041; CHECK-NEXT: vld $vr1, $a2, 042; CHECK-NEXT: vdiv.wu $vr0, $vr0, $vr143; CHECK-NEXT: vst $vr0, $a0, 044; CHECK-NEXT: ret45entry:46 %v0 = load <4 x i32>, ptr %a047 %v1 = load <4 x i32>, ptr %a148 %v2 = udiv <4 x i32> %v0, %v149 store <4 x i32> %v2, ptr %res50 ret void51}52 53define void @udiv_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {54; CHECK-LABEL: udiv_v2i64:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vld $vr0, $a1, 057; CHECK-NEXT: vld $vr1, $a2, 058; CHECK-NEXT: vdiv.du $vr0, $vr0, $vr159; CHECK-NEXT: vst $vr0, $a0, 060; CHECK-NEXT: ret61entry:62 %v0 = load <2 x i64>, ptr %a063 %v1 = load <2 x i64>, ptr %a164 %v2 = udiv <2 x i64> %v0, %v165 store <2 x i64> %v2, ptr %res66 ret void67}68 69define void @udiv_v16i8_8(ptr %res, ptr %a0) nounwind {70; CHECK-LABEL: udiv_v16i8_8:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vld $vr0, $a1, 073; CHECK-NEXT: vsrli.b $vr0, $vr0, 374; CHECK-NEXT: vst $vr0, $a0, 075; CHECK-NEXT: ret76entry:77 %v0 = load <16 x i8>, ptr %a078 %v1 = udiv <16 x i8> %v0, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>79 store <16 x i8> %v1, ptr %res80 ret void81}82 83define void @udiv_v8i16_8(ptr %res, ptr %a0) nounwind {84; CHECK-LABEL: udiv_v8i16_8:85; CHECK: # %bb.0: # %entry86; CHECK-NEXT: vld $vr0, $a1, 087; CHECK-NEXT: vsrli.h $vr0, $vr0, 388; CHECK-NEXT: vst $vr0, $a0, 089; CHECK-NEXT: ret90entry:91 %v0 = load <8 x i16>, ptr %a092 %v1 = udiv <8 x i16> %v0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>93 store <8 x i16> %v1, ptr %res94 ret void95}96 97define void @udiv_v4i32_8(ptr %res, ptr %a0) nounwind {98; CHECK-LABEL: udiv_v4i32_8:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: vld $vr0, $a1, 0101; CHECK-NEXT: vsrli.w $vr0, $vr0, 3102; CHECK-NEXT: vst $vr0, $a0, 0103; CHECK-NEXT: ret104entry:105 %v0 = load <4 x i32>, ptr %a0106 %v1 = udiv <4 x i32> %v0, <i32 8, i32 8, i32 8, i32 8>107 store <4 x i32> %v1, ptr %res108 ret void109}110 111define void @udiv_v2i64_8(ptr %res, ptr %a0) nounwind {112; CHECK-LABEL: udiv_v2i64_8:113; CHECK: # %bb.0: # %entry114; CHECK-NEXT: vld $vr0, $a1, 0115; CHECK-NEXT: vsrli.d $vr0, $vr0, 3116; CHECK-NEXT: vst $vr0, $a0, 0117; CHECK-NEXT: ret118entry:119 %v0 = load <2 x i64>, ptr %a0120 %v1 = udiv <2 x i64> %v0, <i64 8, i64 8>121 store <2 x i64> %v1, ptr %res122 ret void123}124