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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5define <4 x i32> @xor_shl_splat_vec_one(i32 %x, <4 x i32> %y) nounwind {6; CHECK-LABEL: xor_shl_splat_vec_one:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vreplgr2vr.w $vr1, $a09; CHECK-NEXT: vsll.w $vr0, $vr1, $vr010; CHECK-NEXT: vbitrevi.w $vr0, $vr0, 011; CHECK-NEXT: ret12entry:13 %ins = insertelement <4 x i32> poison, i32 %x, i64 014 %splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer15 %shl = shl <4 x i32> %splat, %y16 %xor = xor <4 x i32> %shl, splat (i32 1)17 ret <4 x i32> %xor18}19