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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx %s -o - | FileCheck %s --check-prefix=LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s --check-prefix=LA644 5define void @vec_reduce_add_v16i8(ptr %src, ptr %dst) nounwind {6; LA32-LABEL: vec_reduce_add_v16i8:7; LA32: # %bb.0:8; LA32-NEXT: vld $vr0, $a0, 09; LA32-NEXT: vhaddw.h.b $vr0, $vr0, $vr010; LA32-NEXT: vhaddw.w.h $vr0, $vr0, $vr011; LA32-NEXT: vhaddw.d.w $vr0, $vr0, $vr012; LA32-NEXT: vhaddw.q.d $vr0, $vr0, $vr013; LA32-NEXT: vpickve2gr.w $a0, $vr0, 014; LA32-NEXT: st.b $a0, $a1, 015; LA32-NEXT: ret16;17; LA64-LABEL: vec_reduce_add_v16i8:18; LA64: # %bb.0:19; LA64-NEXT: vld $vr0, $a0, 020; LA64-NEXT: vhaddw.h.b $vr0, $vr0, $vr021; LA64-NEXT: vhaddw.w.h $vr0, $vr0, $vr022; LA64-NEXT: vhaddw.d.w $vr0, $vr0, $vr023; LA64-NEXT: vhaddw.q.d $vr0, $vr0, $vr024; LA64-NEXT: vpickve2gr.d $a0, $vr0, 025; LA64-NEXT: st.b $a0, $a1, 026; LA64-NEXT: ret27 %v = load <16 x i8>, ptr %src28 %res = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %v)29 store i8 %res, ptr %dst30 ret void31}32 33define void @vec_reduce_add_v8i8(ptr %src, ptr %dst) nounwind {34; LA32-LABEL: vec_reduce_add_v8i8:35; LA32: # %bb.0:36; LA32-NEXT: ld.w $a2, $a0, 037; LA32-NEXT: ld.w $a0, $a0, 438; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 039; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 140; LA32-NEXT: vhaddw.h.b $vr0, $vr0, $vr041; LA32-NEXT: vhaddw.w.h $vr0, $vr0, $vr042; LA32-NEXT: vhaddw.d.w $vr0, $vr0, $vr043; LA32-NEXT: vpickve2gr.w $a0, $vr0, 044; LA32-NEXT: st.b $a0, $a1, 045; LA32-NEXT: ret46;47; LA64-LABEL: vec_reduce_add_v8i8:48; LA64: # %bb.0:49; LA64-NEXT: ld.d $a0, $a0, 050; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 051; LA64-NEXT: vhaddw.h.b $vr0, $vr0, $vr052; LA64-NEXT: vhaddw.w.h $vr0, $vr0, $vr053; LA64-NEXT: vhaddw.d.w $vr0, $vr0, $vr054; LA64-NEXT: vpickve2gr.d $a0, $vr0, 055; LA64-NEXT: st.b $a0, $a1, 056; LA64-NEXT: ret57 %v = load <8 x i8>, ptr %src58 %res = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %v)59 store i8 %res, ptr %dst60 ret void61}62 63define void @vec_reduce_add_v4i8(ptr %src, ptr %dst) nounwind {64; LA32-LABEL: vec_reduce_add_v4i8:65; LA32: # %bb.0:66; LA32-NEXT: ld.w $a0, $a0, 067; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 068; LA32-NEXT: vhaddw.h.b $vr0, $vr0, $vr069; LA32-NEXT: vhaddw.w.h $vr0, $vr0, $vr070; LA32-NEXT: vpickve2gr.w $a0, $vr0, 071; LA32-NEXT: st.b $a0, $a1, 072; LA32-NEXT: ret73;74; LA64-LABEL: vec_reduce_add_v4i8:75; LA64: # %bb.0:76; LA64-NEXT: ld.w $a0, $a0, 077; LA64-NEXT: vinsgr2vr.w $vr0, $a0, 078; LA64-NEXT: vhaddw.h.b $vr0, $vr0, $vr079; LA64-NEXT: vhaddw.w.h $vr0, $vr0, $vr080; LA64-NEXT: vpickve2gr.d $a0, $vr0, 081; LA64-NEXT: st.b $a0, $a1, 082; LA64-NEXT: ret83 %v = load <4 x i8>, ptr %src84 %res = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %v)85 store i8 %res, ptr %dst86 ret void87}88 89define void @vec_reduce_add_v2i8(ptr %src, ptr %dst) nounwind {90; LA32-LABEL: vec_reduce_add_v2i8:91; LA32: # %bb.0:92; LA32-NEXT: ld.h $a0, $a0, 093; LA32-NEXT: vinsgr2vr.h $vr0, $a0, 094; LA32-NEXT: vhaddw.h.b $vr0, $vr0, $vr095; LA32-NEXT: vpickve2gr.w $a0, $vr0, 096; LA32-NEXT: st.b $a0, $a1, 097; LA32-NEXT: ret98;99; LA64-LABEL: vec_reduce_add_v2i8:100; LA64: # %bb.0:101; LA64-NEXT: ld.h $a0, $a0, 0102; LA64-NEXT: vinsgr2vr.h $vr0, $a0, 0103; LA64-NEXT: vhaddw.h.b $vr0, $vr0, $vr0104; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0105; LA64-NEXT: st.b $a0, $a1, 0106; LA64-NEXT: ret107 %v = load <2 x i8>, ptr %src108 %res = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> %v)109 store i8 %res, ptr %dst110 ret void111}112 113define void @vec_reduce_add_v8i16(ptr %src, ptr %dst) nounwind {114; LA32-LABEL: vec_reduce_add_v8i16:115; LA32: # %bb.0:116; LA32-NEXT: vld $vr0, $a0, 0117; LA32-NEXT: vhaddw.w.h $vr0, $vr0, $vr0118; LA32-NEXT: vhaddw.d.w $vr0, $vr0, $vr0119; LA32-NEXT: vhaddw.q.d $vr0, $vr0, $vr0120; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0121; LA32-NEXT: st.h $a0, $a1, 0122; LA32-NEXT: ret123;124; LA64-LABEL: vec_reduce_add_v8i16:125; LA64: # %bb.0:126; LA64-NEXT: vld $vr0, $a0, 0127; LA64-NEXT: vhaddw.w.h $vr0, $vr0, $vr0128; LA64-NEXT: vhaddw.d.w $vr0, $vr0, $vr0129; LA64-NEXT: vhaddw.q.d $vr0, $vr0, $vr0130; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0131; LA64-NEXT: st.h $a0, $a1, 0132; LA64-NEXT: ret133 %v = load <8 x i16>, ptr %src134 %res = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %v)135 store i16 %res, ptr %dst136 ret void137}138 139define void @vec_reduce_add_v4i16(ptr %src, ptr %dst) nounwind {140; LA32-LABEL: vec_reduce_add_v4i16:141; LA32: # %bb.0:142; LA32-NEXT: ld.w $a2, $a0, 0143; LA32-NEXT: ld.w $a0, $a0, 4144; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0145; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1146; LA32-NEXT: vhaddw.w.h $vr0, $vr0, $vr0147; LA32-NEXT: vhaddw.d.w $vr0, $vr0, $vr0148; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0149; LA32-NEXT: st.h $a0, $a1, 0150; LA32-NEXT: ret151;152; LA64-LABEL: vec_reduce_add_v4i16:153; LA64: # %bb.0:154; LA64-NEXT: ld.d $a0, $a0, 0155; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0156; LA64-NEXT: vhaddw.w.h $vr0, $vr0, $vr0157; LA64-NEXT: vhaddw.d.w $vr0, $vr0, $vr0158; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0159; LA64-NEXT: st.h $a0, $a1, 0160; LA64-NEXT: ret161 %v = load <4 x i16>, ptr %src162 %res = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %v)163 store i16 %res, ptr %dst164 ret void165}166 167define void @vec_reduce_add_v2i16(ptr %src, ptr %dst) nounwind {168; LA32-LABEL: vec_reduce_add_v2i16:169; LA32: # %bb.0:170; LA32-NEXT: ld.w $a0, $a0, 0171; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 0172; LA32-NEXT: vhaddw.w.h $vr0, $vr0, $vr0173; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0174; LA32-NEXT: st.h $a0, $a1, 0175; LA32-NEXT: ret176;177; LA64-LABEL: vec_reduce_add_v2i16:178; LA64: # %bb.0:179; LA64-NEXT: ld.w $a0, $a0, 0180; LA64-NEXT: vinsgr2vr.w $vr0, $a0, 0181; LA64-NEXT: vhaddw.w.h $vr0, $vr0, $vr0182; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0183; LA64-NEXT: st.h $a0, $a1, 0184; LA64-NEXT: ret185 %v = load <2 x i16>, ptr %src186 %res = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %v)187 store i16 %res, ptr %dst188 ret void189}190 191define void @vec_reduce_add_v4i32(ptr %src, ptr %dst) nounwind {192; LA32-LABEL: vec_reduce_add_v4i32:193; LA32: # %bb.0:194; LA32-NEXT: vld $vr0, $a0, 0195; LA32-NEXT: vhaddw.d.w $vr0, $vr0, $vr0196; LA32-NEXT: vhaddw.q.d $vr0, $vr0, $vr0197; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0198; LA32-NEXT: st.w $a0, $a1, 0199; LA32-NEXT: ret200;201; LA64-LABEL: vec_reduce_add_v4i32:202; LA64: # %bb.0:203; LA64-NEXT: vld $vr0, $a0, 0204; LA64-NEXT: vhaddw.d.w $vr0, $vr0, $vr0205; LA64-NEXT: vhaddw.q.d $vr0, $vr0, $vr0206; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0207; LA64-NEXT: st.w $a0, $a1, 0208; LA64-NEXT: ret209 %v = load <4 x i32>, ptr %src210 %res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v)211 store i32 %res, ptr %dst212 ret void213}214 215define void @vec_reduce_add_v2i32(ptr %src, ptr %dst) nounwind {216; LA32-LABEL: vec_reduce_add_v2i32:217; LA32: # %bb.0:218; LA32-NEXT: ld.w $a2, $a0, 0219; LA32-NEXT: ld.w $a0, $a0, 4220; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0221; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1222; LA32-NEXT: vhaddw.d.w $vr0, $vr0, $vr0223; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0224; LA32-NEXT: st.w $a0, $a1, 0225; LA32-NEXT: ret226;227; LA64-LABEL: vec_reduce_add_v2i32:228; LA64: # %bb.0:229; LA64-NEXT: ld.d $a0, $a0, 0230; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0231; LA64-NEXT: vhaddw.d.w $vr0, $vr0, $vr0232; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0233; LA64-NEXT: st.w $a0, $a1, 0234; LA64-NEXT: ret235 %v = load <2 x i32>, ptr %src236 %res = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %v)237 store i32 %res, ptr %dst238 ret void239}240 241define void @vec_reduce_add_v2i64(ptr %src, ptr %dst) nounwind {242; LA32-LABEL: vec_reduce_add_v2i64:243; LA32: # %bb.0:244; LA32-NEXT: vld $vr0, $a0, 0245; LA32-NEXT: vpickve2gr.w $a0, $vr0, 2246; LA32-NEXT: vpickve2gr.w $a2, $vr0, 0247; LA32-NEXT: vpickve2gr.w $a3, $vr0, 3248; LA32-NEXT: vpickve2gr.w $a4, $vr0, 1249; LA32-NEXT: add.w $a3, $a4, $a3250; LA32-NEXT: add.w $a0, $a2, $a0251; LA32-NEXT: sltu $a2, $a0, $a2252; LA32-NEXT: add.w $a2, $a3, $a2253; LA32-NEXT: st.w $a0, $a1, 0254; LA32-NEXT: st.w $a2, $a1, 4255; LA32-NEXT: ret256;257; LA64-LABEL: vec_reduce_add_v2i64:258; LA64: # %bb.0:259; LA64-NEXT: vld $vr0, $a0, 0260; LA64-NEXT: vhaddw.q.d $vr0, $vr0, $vr0261; LA64-NEXT: vstelm.d $vr0, $a1, 0, 0262; LA64-NEXT: ret263 %v = load <2 x i64>, ptr %src264 %res = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %v)265 store i64 %res, ptr %dst266 ret void267}268