235 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA644 5define void @vec_reduce_and_v16i8(ptr %src, ptr %dst) nounwind {6; CHECK-LABEL: vec_reduce_and_v16i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vld $vr0, $a0, 09; CHECK-NEXT: vbsrl.v $vr1, $vr0, 810; CHECK-NEXT: vand.v $vr0, $vr1, $vr011; CHECK-NEXT: vbsrl.v $vr1, $vr0, 412; CHECK-NEXT: vand.v $vr0, $vr1, $vr013; CHECK-NEXT: vbsrl.v $vr1, $vr0, 214; CHECK-NEXT: vand.v $vr0, $vr1, $vr015; CHECK-NEXT: vbsrl.v $vr1, $vr0, 116; CHECK-NEXT: vand.v $vr0, $vr1, $vr017; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 018; CHECK-NEXT: ret19 %v = load <16 x i8>, ptr %src20 %res = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %v)21 store i8 %res, ptr %dst22 ret void23}24 25define void @vec_reduce_and_v8i8(ptr %src, ptr %dst) nounwind {26; LA32-LABEL: vec_reduce_and_v8i8:27; LA32: # %bb.0:28; LA32-NEXT: ld.w $a2, $a0, 029; LA32-NEXT: ld.w $a0, $a0, 430; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 031; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 132; LA32-NEXT: vbsrl.v $vr1, $vr0, 433; LA32-NEXT: vand.v $vr0, $vr1, $vr034; LA32-NEXT: vbsrl.v $vr1, $vr0, 235; LA32-NEXT: vand.v $vr0, $vr1, $vr036; LA32-NEXT: vbsrl.v $vr1, $vr0, 137; LA32-NEXT: vand.v $vr0, $vr1, $vr038; LA32-NEXT: vstelm.b $vr0, $a1, 0, 039; LA32-NEXT: ret40;41; LA64-LABEL: vec_reduce_and_v8i8:42; LA64: # %bb.0:43; LA64-NEXT: ld.d $a0, $a0, 044; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 045; LA64-NEXT: vbsrl.v $vr1, $vr0, 446; LA64-NEXT: vand.v $vr0, $vr1, $vr047; LA64-NEXT: vbsrl.v $vr1, $vr0, 248; LA64-NEXT: vand.v $vr0, $vr1, $vr049; LA64-NEXT: vbsrl.v $vr1, $vr0, 150; LA64-NEXT: vand.v $vr0, $vr1, $vr051; LA64-NEXT: vstelm.b $vr0, $a1, 0, 052; LA64-NEXT: ret53 %v = load <8 x i8>, ptr %src54 %res = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %v)55 store i8 %res, ptr %dst56 ret void57}58 59define void @vec_reduce_and_v4i8(ptr %src, ptr %dst) nounwind {60; CHECK-LABEL: vec_reduce_and_v4i8:61; CHECK: # %bb.0:62; CHECK-NEXT: ld.w $a0, $a0, 063; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 064; CHECK-NEXT: vbsrl.v $vr1, $vr0, 265; CHECK-NEXT: vand.v $vr0, $vr1, $vr066; CHECK-NEXT: vbsrl.v $vr1, $vr0, 167; CHECK-NEXT: vand.v $vr0, $vr1, $vr068; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 069; CHECK-NEXT: ret70 %v = load <4 x i8>, ptr %src71 %res = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %v)72 store i8 %res, ptr %dst73 ret void74}75 76define void @vec_reduce_and_v2i8(ptr %src, ptr %dst) nounwind {77; CHECK-LABEL: vec_reduce_and_v2i8:78; CHECK: # %bb.0:79; CHECK-NEXT: ld.h $a0, $a0, 080; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 081; CHECK-NEXT: vbsrl.v $vr1, $vr0, 182; CHECK-NEXT: vand.v $vr0, $vr1, $vr083; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 084; CHECK-NEXT: ret85 %v = load <2 x i8>, ptr %src86 %res = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> %v)87 store i8 %res, ptr %dst88 ret void89}90 91define void @vec_reduce_and_v8i16(ptr %src, ptr %dst) nounwind {92; CHECK-LABEL: vec_reduce_and_v8i16:93; CHECK: # %bb.0:94; CHECK-NEXT: vld $vr0, $a0, 095; CHECK-NEXT: vbsrl.v $vr1, $vr0, 896; CHECK-NEXT: vand.v $vr0, $vr1, $vr097; CHECK-NEXT: vbsrl.v $vr1, $vr0, 498; CHECK-NEXT: vand.v $vr0, $vr1, $vr099; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2100; CHECK-NEXT: vand.v $vr0, $vr1, $vr0101; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0102; CHECK-NEXT: ret103 %v = load <8 x i16>, ptr %src104 %res = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %v)105 store i16 %res, ptr %dst106 ret void107}108 109define void @vec_reduce_and_v4i16(ptr %src, ptr %dst) nounwind {110; LA32-LABEL: vec_reduce_and_v4i16:111; LA32: # %bb.0:112; LA32-NEXT: ld.w $a2, $a0, 0113; LA32-NEXT: ld.w $a0, $a0, 4114; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0115; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1116; LA32-NEXT: vbsrl.v $vr1, $vr0, 4117; LA32-NEXT: vand.v $vr0, $vr1, $vr0118; LA32-NEXT: vbsrl.v $vr1, $vr0, 2119; LA32-NEXT: vand.v $vr0, $vr1, $vr0120; LA32-NEXT: vstelm.h $vr0, $a1, 0, 0121; LA32-NEXT: ret122;123; LA64-LABEL: vec_reduce_and_v4i16:124; LA64: # %bb.0:125; LA64-NEXT: ld.d $a0, $a0, 0126; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0127; LA64-NEXT: vbsrl.v $vr1, $vr0, 4128; LA64-NEXT: vand.v $vr0, $vr1, $vr0129; LA64-NEXT: vbsrl.v $vr1, $vr0, 2130; LA64-NEXT: vand.v $vr0, $vr1, $vr0131; LA64-NEXT: vstelm.h $vr0, $a1, 0, 0132; LA64-NEXT: ret133 %v = load <4 x i16>, ptr %src134 %res = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v)135 store i16 %res, ptr %dst136 ret void137}138 139define void @vec_reduce_and_v2i16(ptr %src, ptr %dst) nounwind {140; CHECK-LABEL: vec_reduce_and_v2i16:141; CHECK: # %bb.0:142; CHECK-NEXT: ld.w $a0, $a0, 0143; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0144; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2145; CHECK-NEXT: vand.v $vr0, $vr1, $vr0146; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0147; CHECK-NEXT: ret148 %v = load <2 x i16>, ptr %src149 %res = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %v)150 store i16 %res, ptr %dst151 ret void152}153 154define void @vec_reduce_and_v4i32(ptr %src, ptr %dst) nounwind {155; LA32-LABEL: vec_reduce_and_v4i32:156; LA32: # %bb.0:157; LA32-NEXT: vld $vr0, $a0, 0158; LA32-NEXT: vbsrl.v $vr1, $vr0, 8159; LA32-NEXT: vand.v $vr0, $vr1, $vr0160; LA32-NEXT: vbsrl.v $vr1, $vr0, 4161; LA32-NEXT: vand.v $vr0, $vr1, $vr0162; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0163; LA32-NEXT: st.w $a0, $a1, 0164; LA32-NEXT: ret165;166; LA64-LABEL: vec_reduce_and_v4i32:167; LA64: # %bb.0:168; LA64-NEXT: vld $vr0, $a0, 0169; LA64-NEXT: vbsrl.v $vr1, $vr0, 8170; LA64-NEXT: vand.v $vr0, $vr1, $vr0171; LA64-NEXT: vbsrl.v $vr1, $vr0, 4172; LA64-NEXT: vand.v $vr0, $vr1, $vr0173; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0174; LA64-NEXT: ret175 %v = load <4 x i32>, ptr %src176 %res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %v)177 store i32 %res, ptr %dst178 ret void179}180 181define void @vec_reduce_and_v2i32(ptr %src, ptr %dst) nounwind {182; LA32-LABEL: vec_reduce_and_v2i32:183; LA32: # %bb.0:184; LA32-NEXT: ld.w $a2, $a0, 0185; LA32-NEXT: ld.w $a0, $a0, 4186; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0187; LA32-NEXT: vori.b $vr1, $vr0, 0188; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1189; LA32-NEXT: vbsrl.v $vr1, $vr1, 4190; LA32-NEXT: vand.v $vr0, $vr1, $vr0191; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0192; LA32-NEXT: st.w $a0, $a1, 0193; LA32-NEXT: ret194;195; LA64-LABEL: vec_reduce_and_v2i32:196; LA64: # %bb.0:197; LA64-NEXT: ld.d $a0, $a0, 0198; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0199; LA64-NEXT: vbsrl.v $vr1, $vr0, 4200; LA64-NEXT: vand.v $vr0, $vr1, $vr0201; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0202; LA64-NEXT: ret203 %v = load <2 x i32>, ptr %src204 %res = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %v)205 store i32 %res, ptr %dst206 ret void207}208 209define void @vec_reduce_and_v2i64(ptr %src, ptr %dst) nounwind {210; LA32-LABEL: vec_reduce_and_v2i64:211; LA32: # %bb.0:212; LA32-NEXT: vld $vr0, $a0, 0213; LA32-NEXT: vpickve2gr.w $a0, $vr0, 3214; LA32-NEXT: vpickve2gr.w $a2, $vr0, 1215; LA32-NEXT: vpickve2gr.w $a3, $vr0, 2216; LA32-NEXT: vpickve2gr.w $a4, $vr0, 0217; LA32-NEXT: and $a3, $a4, $a3218; LA32-NEXT: and $a0, $a2, $a0219; LA32-NEXT: st.w $a0, $a1, 4220; LA32-NEXT: st.w $a3, $a1, 0221; LA32-NEXT: ret222;223; LA64-LABEL: vec_reduce_and_v2i64:224; LA64: # %bb.0:225; LA64-NEXT: vld $vr0, $a0, 0226; LA64-NEXT: vbsrl.v $vr1, $vr0, 8227; LA64-NEXT: vand.v $vr0, $vr1, $vr0228; LA64-NEXT: vstelm.d $vr0, $a1, 0, 0229; LA64-NEXT: ret230 %v = load <2 x i64>, ptr %src231 %res = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %v)232 store i64 %res, ptr %dst233 ret void234}235