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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA644 5define void @load_sext_2i8_to_2i64(ptr %ptr, ptr %dst) {6; CHECK-LABEL: load_sext_2i8_to_2i64:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: ld.h $a0, $a0, 09; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 010; CHECK-NEXT: vilvl.b $vr0, $vr0, $vr011; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr012; CHECK-NEXT: vilvl.w $vr0, $vr0, $vr013; CHECK-NEXT: vslli.d $vr0, $vr0, 5614; CHECK-NEXT: vsrai.d $vr0, $vr0, 5615; CHECK-NEXT: vst $vr0, $a1, 016; CHECK-NEXT: ret17entry:18 %A = load <2 x i8>, ptr %ptr19 %B = sext <2 x i8> %A to <2 x i64>20 store <2 x i64> %B, ptr %dst21 ret void22}23 24define void @load_sext_4i8_to_4i32(ptr %ptr, ptr %dst) {25; CHECK-LABEL: load_sext_4i8_to_4i32:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: ld.w $a0, $a0, 028; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 029; CHECK-NEXT: vilvl.b $vr0, $vr0, $vr030; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr031; CHECK-NEXT: vslli.w $vr0, $vr0, 2432; CHECK-NEXT: vsrai.w $vr0, $vr0, 2433; CHECK-NEXT: vst $vr0, $a1, 034; CHECK-NEXT: ret35entry:36 %A = load <4 x i8>, ptr %ptr37 %B = sext <4 x i8> %A to <4 x i32>38 store <4 x i32> %B, ptr %dst39 ret void40}41 42define void @load_sext_8i8_to_8i16(ptr %ptr, ptr %dst) {43; LA32-LABEL: load_sext_8i8_to_8i16:44; LA32: # %bb.0: # %entry45; LA32-NEXT: ld.w $a2, $a0, 046; LA32-NEXT: ld.w $a0, $a0, 447; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 048; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 149; LA32-NEXT: vilvl.b $vr0, $vr0, $vr050; LA32-NEXT: vslli.h $vr0, $vr0, 851; LA32-NEXT: vsrai.h $vr0, $vr0, 852; LA32-NEXT: vst $vr0, $a1, 053; LA32-NEXT: ret54;55; LA64-LABEL: load_sext_8i8_to_8i16:56; LA64: # %bb.0: # %entry57; LA64-NEXT: ld.d $a0, $a0, 058; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 059; LA64-NEXT: vilvl.b $vr0, $vr0, $vr060; LA64-NEXT: vslli.h $vr0, $vr0, 861; LA64-NEXT: vsrai.h $vr0, $vr0, 862; LA64-NEXT: vst $vr0, $a1, 063; LA64-NEXT: ret64entry:65 %A = load <8 x i8>, ptr %ptr66 %B = sext <8 x i8> %A to <8 x i16>67 store <8 x i16> %B, ptr %dst68 ret void69}70 71define void @load_sext_2i16_to_2i64(ptr %ptr, ptr %dst) {72; CHECK-LABEL: load_sext_2i16_to_2i64:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: ld.w $a0, $a0, 075; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 076; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr077; CHECK-NEXT: vilvl.w $vr0, $vr0, $vr078; CHECK-NEXT: vslli.d $vr0, $vr0, 4879; CHECK-NEXT: vsrai.d $vr0, $vr0, 4880; CHECK-NEXT: vst $vr0, $a1, 081; CHECK-NEXT: ret82entry:83 %A = load <2 x i16>, ptr %ptr84 %B = sext <2 x i16> %A to <2 x i64>85 store <2 x i64> %B, ptr %dst86 ret void87}88 89define void @load_sext_4i16_to_4i32(ptr %ptr, ptr %dst) {90; LA32-LABEL: load_sext_4i16_to_4i32:91; LA32: # %bb.0: # %entry92; LA32-NEXT: ld.w $a2, $a0, 093; LA32-NEXT: ld.w $a0, $a0, 494; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 095; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 196; LA32-NEXT: vilvl.h $vr0, $vr0, $vr097; LA32-NEXT: vslli.w $vr0, $vr0, 1698; LA32-NEXT: vsrai.w $vr0, $vr0, 1699; LA32-NEXT: vst $vr0, $a1, 0100; LA32-NEXT: ret101;102; LA64-LABEL: load_sext_4i16_to_4i32:103; LA64: # %bb.0: # %entry104; LA64-NEXT: ld.d $a0, $a0, 0105; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0106; LA64-NEXT: vilvl.h $vr0, $vr0, $vr0107; LA64-NEXT: vslli.w $vr0, $vr0, 16108; LA64-NEXT: vsrai.w $vr0, $vr0, 16109; LA64-NEXT: vst $vr0, $a1, 0110; LA64-NEXT: ret111entry:112 %A = load <4 x i16>, ptr %ptr113 %B = sext <4 x i16> %A to <4 x i32>114 store <4 x i32> %B, ptr %dst115 ret void116}117 118define void @load_sext_2i32_to_2i64(ptr %ptr, ptr %dst) {119; LA32-LABEL: load_sext_2i32_to_2i64:120; LA32: # %bb.0: # %entry121; LA32-NEXT: ld.w $a2, $a0, 0122; LA32-NEXT: ld.w $a0, $a0, 4123; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0124; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2125; LA32-NEXT: vslli.d $vr0, $vr0, 32126; LA32-NEXT: vsrai.d $vr0, $vr0, 32127; LA32-NEXT: vst $vr0, $a1, 0128; LA32-NEXT: ret129;130; LA64-LABEL: load_sext_2i32_to_2i64:131; LA64: # %bb.0: # %entry132; LA64-NEXT: ld.d $a0, $a0, 0133; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0134; LA64-NEXT: vshuf4i.w $vr0, $vr0, 16135; LA64-NEXT: vslli.d $vr0, $vr0, 32136; LA64-NEXT: vsrai.d $vr0, $vr0, 32137; LA64-NEXT: vst $vr0, $a1, 0138; LA64-NEXT: ret139entry:140 %A = load <2 x i32>, ptr %ptr141 %B = sext <2 x i32> %A to <2 x i64>142 store <2 x i64> %B, ptr %dst143 ret void144}145 146define void @load_sext_16i8_to_16i16(ptr %ptr, ptr %dst) {147; CHECK-LABEL: load_sext_16i8_to_16i16:148; CHECK: # %bb.0: # %entry149; CHECK-NEXT: vld $vr0, $a0, 0150; CHECK-NEXT: vilvl.b $vr1, $vr0, $vr0151; CHECK-NEXT: vslli.h $vr1, $vr1, 8152; CHECK-NEXT: vsrai.h $vr1, $vr1, 8153; CHECK-NEXT: vilvh.b $vr0, $vr0, $vr0154; CHECK-NEXT: vslli.h $vr0, $vr0, 8155; CHECK-NEXT: vsrai.h $vr0, $vr0, 8156; CHECK-NEXT: vst $vr0, $a1, 16157; CHECK-NEXT: vst $vr1, $a1, 0158; CHECK-NEXT: ret159entry:160 %A = load <16 x i8>, ptr %ptr161 %B = sext <16 x i8> %A to <16 x i16>162 store <16 x i16> %B, ptr %dst163 ret void164}165 166define void @load_sext_16i8_to_16i32(ptr %ptr, ptr %dst) {167; CHECK-LABEL: load_sext_16i8_to_16i32:168; CHECK: # %bb.0: # %entry169; CHECK-NEXT: vld $vr0, $a0, 0170; CHECK-NEXT: vilvl.b $vr1, $vr0, $vr0171; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr1172; CHECK-NEXT: vslli.w $vr2, $vr2, 24173; CHECK-NEXT: vsrai.w $vr2, $vr2, 24174; CHECK-NEXT: vilvh.h $vr1, $vr1, $vr1175; CHECK-NEXT: vslli.w $vr1, $vr1, 24176; CHECK-NEXT: vsrai.w $vr1, $vr1, 24177; CHECK-NEXT: vilvh.b $vr0, $vr0, $vr0178; CHECK-NEXT: vilvl.h $vr3, $vr0, $vr0179; CHECK-NEXT: vslli.w $vr3, $vr3, 24180; CHECK-NEXT: vsrai.w $vr3, $vr3, 24181; CHECK-NEXT: vilvh.h $vr0, $vr0, $vr0182; CHECK-NEXT: vslli.w $vr0, $vr0, 24183; CHECK-NEXT: vsrai.w $vr0, $vr0, 24184; CHECK-NEXT: vst $vr0, $a1, 48185; CHECK-NEXT: vst $vr3, $a1, 32186; CHECK-NEXT: vst $vr1, $a1, 16187; CHECK-NEXT: vst $vr2, $a1, 0188; CHECK-NEXT: ret189entry:190 %A = load <16 x i8>, ptr %ptr191 %B = sext <16 x i8> %A to <16 x i32>192 store <16 x i32> %B, ptr %dst193 ret void194}195 196define void @load_sext_16i8_to_16i64(ptr %ptr, ptr %dst) {197; CHECK-LABEL: load_sext_16i8_to_16i64:198; CHECK: # %bb.0: # %entry199; CHECK-NEXT: vld $vr0, $a0, 0200; CHECK-NEXT: vilvl.b $vr1, $vr0, $vr0201; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr1202; CHECK-NEXT: vilvl.w $vr3, $vr2, $vr2203; CHECK-NEXT: vslli.d $vr3, $vr3, 56204; CHECK-NEXT: vsrai.d $vr3, $vr3, 56205; CHECK-NEXT: vilvh.w $vr2, $vr2, $vr2206; CHECK-NEXT: vslli.d $vr2, $vr2, 56207; CHECK-NEXT: vsrai.d $vr2, $vr2, 56208; CHECK-NEXT: vilvh.h $vr1, $vr1, $vr1209; CHECK-NEXT: vilvl.w $vr4, $vr1, $vr1210; CHECK-NEXT: vslli.d $vr4, $vr4, 56211; CHECK-NEXT: vsrai.d $vr4, $vr4, 56212; CHECK-NEXT: vilvh.w $vr1, $vr1, $vr1213; CHECK-NEXT: vslli.d $vr1, $vr1, 56214; CHECK-NEXT: vsrai.d $vr1, $vr1, 56215; CHECK-NEXT: vilvh.b $vr0, $vr0, $vr0216; CHECK-NEXT: vilvl.h $vr5, $vr0, $vr0217; CHECK-NEXT: vilvl.w $vr6, $vr5, $vr5218; CHECK-NEXT: vslli.d $vr6, $vr6, 56219; CHECK-NEXT: vsrai.d $vr6, $vr6, 56220; CHECK-NEXT: vilvh.w $vr5, $vr5, $vr5221; CHECK-NEXT: vslli.d $vr5, $vr5, 56222; CHECK-NEXT: vsrai.d $vr5, $vr5, 56223; CHECK-NEXT: vilvh.h $vr0, $vr0, $vr0224; CHECK-NEXT: vilvl.w $vr7, $vr0, $vr0225; CHECK-NEXT: vslli.d $vr7, $vr7, 56226; CHECK-NEXT: vsrai.d $vr7, $vr7, 56227; CHECK-NEXT: vilvh.w $vr0, $vr0, $vr0228; CHECK-NEXT: vslli.d $vr0, $vr0, 56229; CHECK-NEXT: vsrai.d $vr0, $vr0, 56230; CHECK-NEXT: vst $vr0, $a1, 112231; CHECK-NEXT: vst $vr7, $a1, 96232; CHECK-NEXT: vst $vr5, $a1, 80233; CHECK-NEXT: vst $vr6, $a1, 64234; CHECK-NEXT: vst $vr1, $a1, 48235; CHECK-NEXT: vst $vr4, $a1, 32236; CHECK-NEXT: vst $vr2, $a1, 16237; CHECK-NEXT: vst $vr3, $a1, 0238; CHECK-NEXT: ret239entry:240 %A = load <16 x i8>, ptr %ptr241 %B = sext <16 x i8> %A to <16 x i64>242 store <16 x i64> %B, ptr %dst243 ret void244}245 246define void @load_sext_8i16_to_8i32(ptr %ptr, ptr %dst) {247; CHECK-LABEL: load_sext_8i16_to_8i32:248; CHECK: # %bb.0: # %entry249; CHECK-NEXT: vld $vr0, $a0, 0250; CHECK-NEXT: vilvl.h $vr1, $vr0, $vr0251; CHECK-NEXT: vslli.w $vr1, $vr1, 16252; CHECK-NEXT: vsrai.w $vr1, $vr1, 16253; CHECK-NEXT: vilvh.h $vr0, $vr0, $vr0254; CHECK-NEXT: vslli.w $vr0, $vr0, 16255; CHECK-NEXT: vsrai.w $vr0, $vr0, 16256; CHECK-NEXT: vst $vr0, $a1, 16257; CHECK-NEXT: vst $vr1, $a1, 0258; CHECK-NEXT: ret259entry:260 %A = load <8 x i16>, ptr %ptr261 %B = sext <8 x i16> %A to <8 x i32>262 store <8 x i32> %B, ptr %dst263 ret void264}265 266define void @load_sext_8i16_to_8i64(ptr %ptr, ptr %dst) {267; CHECK-LABEL: load_sext_8i16_to_8i64:268; CHECK: # %bb.0: # %entry269; CHECK-NEXT: vld $vr0, $a0, 0270; CHECK-NEXT: vilvl.h $vr1, $vr0, $vr0271; CHECK-NEXT: vilvl.w $vr2, $vr1, $vr1272; CHECK-NEXT: vslli.d $vr2, $vr2, 48273; CHECK-NEXT: vsrai.d $vr2, $vr2, 48274; CHECK-NEXT: vilvh.w $vr1, $vr1, $vr1275; CHECK-NEXT: vslli.d $vr1, $vr1, 48276; CHECK-NEXT: vsrai.d $vr1, $vr1, 48277; CHECK-NEXT: vilvh.h $vr0, $vr0, $vr0278; CHECK-NEXT: vilvl.w $vr3, $vr0, $vr0279; CHECK-NEXT: vslli.d $vr3, $vr3, 48280; CHECK-NEXT: vsrai.d $vr3, $vr3, 48281; CHECK-NEXT: vilvh.w $vr0, $vr0, $vr0282; CHECK-NEXT: vslli.d $vr0, $vr0, 48283; CHECK-NEXT: vsrai.d $vr0, $vr0, 48284; CHECK-NEXT: vst $vr0, $a1, 48285; CHECK-NEXT: vst $vr3, $a1, 32286; CHECK-NEXT: vst $vr1, $a1, 16287; CHECK-NEXT: vst $vr2, $a1, 0288; CHECK-NEXT: ret289entry:290 %A = load <8 x i16>, ptr %ptr291 %B = sext <8 x i16> %A to <8 x i64>292 store <8 x i64> %B, ptr %dst293 ret void294}295 296define void @load_sext_4i32_to_4i64(ptr %ptr, ptr %dst) {297; CHECK-LABEL: load_sext_4i32_to_4i64:298; CHECK: # %bb.0: # %entry299; CHECK-NEXT: vld $vr0, $a0, 0300; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 16301; CHECK-NEXT: vslli.d $vr1, $vr1, 32302; CHECK-NEXT: vsrai.d $vr1, $vr1, 32303; CHECK-NEXT: vshuf4i.w $vr0, $vr0, 50304; CHECK-NEXT: vslli.d $vr0, $vr0, 32305; CHECK-NEXT: vsrai.d $vr0, $vr0, 32306; CHECK-NEXT: vst $vr0, $a1, 16307; CHECK-NEXT: vst $vr1, $a1, 0308; CHECK-NEXT: ret309entry:310 %A = load <4 x i32>, ptr %ptr311 %B = sext <4 x i32> %A to <4 x i64>312 store <4 x i64> %B, ptr %dst313 ret void314}315