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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5define <16 x i8> @shuffle_to_vslli_h_8(<16 x i8> %a) nounwind {6; CHECK-LABEL: shuffle_to_vslli_h_8:7; CHECK: # %bb.0:8; CHECK-NEXT: vslli.h $vr0, $vr0, 89; CHECK-NEXT: ret10 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 16, i32 2, i32 16, i32 4, i32 16, i32 6, i32 16, i32 8, i32 16, i32 10, i32 16, i32 12, i32 16, i32 14>11 ret <16 x i8> %shuffle12}13 14define <16 x i8> @shuffle_to_vsrli_h_8(<16 x i8> %a) nounwind {15; CHECK-LABEL: shuffle_to_vsrli_h_8:16; CHECK: # %bb.0:17; CHECK-NEXT: vsrli.h $vr0, $vr0, 818; CHECK-NEXT: ret19 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16>20 ret <16 x i8> %shuffle21}22 23define <16 x i8> @shuffle_to_vslli_w_8(<16 x i8> %a) nounwind {24; CHECK-LABEL: shuffle_to_vslli_w_8:25; CHECK: # %bb.0:26; CHECK-NEXT: vslli.w $vr0, $vr0, 827; CHECK-NEXT: ret28 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 1, i32 2, i32 16, i32 4, i32 5, i32 6, i32 16, i32 8, i32 9, i32 10, i32 16, i32 12, i32 13, i32 14>29 ret <16 x i8> %shuffle30}31 32define <16 x i8> @shuffle_to_vsrli_w_8(<16 x i8> %a) nounwind {33; CHECK-LABEL: shuffle_to_vsrli_w_8:34; CHECK: # %bb.0:35; CHECK-NEXT: vsrli.w $vr0, $vr0, 836; CHECK-NEXT: ret37 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 2, i32 3, i32 16, i32 5, i32 6, i32 7, i32 16, i32 9, i32 10, i32 11, i32 16, i32 13, i32 14, i32 15, i32 16>38 ret <16 x i8> %shuffle39}40 41define <8 x i16> @shuffle_to_vslli_w_16(<8 x i16> %a) nounwind {42; CHECK-LABEL: shuffle_to_vslli_w_16:43; CHECK: # %bb.0:44; CHECK-NEXT: vslli.w $vr0, $vr0, 1645; CHECK-NEXT: ret46 %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 0, i32 8, i32 2, i32 8, i32 4, i32 8, i32 6>47 ret <8 x i16> %shuffle48}49 50define <8 x i16> @shuffle_to_vsrli_w_16(<8 x i16> %a) nounwind {51; CHECK-LABEL: shuffle_to_vsrli_w_16:52; CHECK: # %bb.0:53; CHECK-NEXT: vsrli.w $vr0, $vr0, 1654; CHECK-NEXT: ret55 %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 1, i32 8, i32 3, i32 8, i32 5, i32 8, i32 7, i32 8>56 ret <8 x i16> %shuffle57}58 59define <16 x i8> @shuffle_to_vslli_w_24(<16 x i8> %a) nounwind {60; CHECK-LABEL: shuffle_to_vslli_w_24:61; CHECK: # %bb.0:62; CHECK-NEXT: vslli.w $vr0, $vr0, 2463; CHECK-NEXT: ret64 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 12>65 ret <16 x i8> %shuffle66}67 68define <16 x i8> @shuffle_to_vsrli_w_24(<16 x i8> %a) nounwind {69; CHECK-LABEL: shuffle_to_vsrli_w_24:70; CHECK: # %bb.0:71; CHECK-NEXT: vsrli.w $vr0, $vr0, 2472; CHECK-NEXT: ret73 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 3, i32 16, i32 16, i32 16, i32 7, i32 16, i32 16, i32 16, i32 11, i32 16, i32 16, i32 16, i32 15, i32 16, i32 16, i32 16>74 ret <16 x i8> %shuffle75}76 77define <16 x i8> @shuffle_to_vslli_d_8(<16 x i8> %a) nounwind {78; CHECK-LABEL: shuffle_to_vslli_d_8:79; CHECK: # %bb.0:80; CHECK-NEXT: vslli.d $vr0, $vr0, 881; CHECK-NEXT: ret82 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>83 ret <16 x i8> %shuffle84}85 86define <16 x i8> @shuffle_to_vsrli_d_8(<16 x i8> %a) nounwind {87; CHECK-LABEL: shuffle_to_vsrli_d_8:88; CHECK: # %bb.0:89; CHECK-NEXT: vsrli.d $vr0, $vr0, 890; CHECK-NEXT: ret91 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>92 ret <16 x i8> %shuffle93}94 95define <8 x i16> @shuffle_to_vslli_d_16(<8 x i16> %a) nounwind {96; CHECK-LABEL: shuffle_to_vslli_d_16:97; CHECK: # %bb.0:98; CHECK-NEXT: vslli.d $vr0, $vr0, 1699; CHECK-NEXT: ret100 %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 0, i32 1, i32 2, i32 8, i32 4, i32 5, i32 6>101 ret <8 x i16> %shuffle102}103 104define <8 x i16> @shuffle_to_vsrli_d_16(<8 x i16> %a) nounwind {105; CHECK-LABEL: shuffle_to_vsrli_d_16:106; CHECK: # %bb.0:107; CHECK-NEXT: vsrli.d $vr0, $vr0, 16108; CHECK-NEXT: ret109 %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 8>110 ret <8 x i16> %shuffle111}112 113define <16 x i8> @shuffle_to_vslli_d_24(<16 x i8> %a) nounwind {114; CHECK-LABEL: shuffle_to_vslli_d_24:115; CHECK: # %bb.0:116; CHECK-NEXT: vslli.d $vr0, $vr0, 24117; CHECK-NEXT: ret118 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 16, i32 16, i32 8, i32 9, i32 10, i32 11, i32 12>119 ret <16 x i8> %shuffle120}121 122define <16 x i8> @shuffle_to_vsrli_d_24(<16 x i8> %a) nounwind {123; CHECK-LABEL: shuffle_to_vsrli_d_24:124; CHECK: # %bb.0:125; CHECK-NEXT: vsrli.d $vr0, $vr0, 24126; CHECK-NEXT: ret127 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16>128 ret <16 x i8> %shuffle129}130 131define <4 x i32> @shuffle_to_vslli_d_32(<4 x i32> %a) nounwind {132; CHECK-LABEL: shuffle_to_vslli_d_32:133; CHECK: # %bb.0:134; CHECK-NEXT: vslli.d $vr0, $vr0, 32135; CHECK-NEXT: ret136 %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 4, i32 poison>137 ret <4 x i32> %shuffle138}139 140define <4 x i32> @shuffle_to_vsrli_d_32(<4 x i32> %a) nounwind {141; CHECK-LABEL: shuffle_to_vsrli_d_32:142; CHECK: # %bb.0:143; CHECK-NEXT: vsrli.d $vr0, $vr0, 32144; CHECK-NEXT: ret145 %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 4, i32 3, i32 4>146 ret <4 x i32> %shuffle147}148 149define <16 x i8> @shuffle_to_vslli_d_40(<16 x i8> %a) nounwind {150; CHECK-LABEL: shuffle_to_vslli_d_40:151; CHECK: # %bb.0:152; CHECK-NEXT: vslli.d $vr0, $vr0, 40153; CHECK-NEXT: ret154 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8, i32 9, i32 10>155 ret <16 x i8> %shuffle156}157 158define <16 x i8> @shuffle_to_vsrli_d_40(<16 x i8> %a) nounwind {159; CHECK-LABEL: shuffle_to_vsrli_d_40:160; CHECK: # %bb.0:161; CHECK-NEXT: vsrli.d $vr0, $vr0, 40162; CHECK-NEXT: ret163 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16>164 ret <16 x i8> %shuffle165}166 167define <8 x i16> @shuffle_to_vslli_d_48(<8 x i16> %a) nounwind {168; CHECK-LABEL: shuffle_to_vslli_d_48:169; CHECK: # %bb.0:170; CHECK-NEXT: vslli.d $vr0, $vr0, 48171; CHECK-NEXT: ret172 %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 8, i32 8, i32 0, i32 8, i32 8, i32 8, i32 4>173 ret <8 x i16> %shuffle174}175 176define <8 x i16> @shuffle_to_vsrli_d_48(<8 x i16> %a) nounwind {177; CHECK-LABEL: shuffle_to_vsrli_d_48:178; CHECK: # %bb.0:179; CHECK-NEXT: vsrli.d $vr0, $vr0, 48180; CHECK-NEXT: ret181 %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 3, i32 8, i32 8, i32 8, i32 7, i32 8, i32 8, i32 8>182 ret <8 x i16> %shuffle183}184 185define <16 x i8> @shuffle_to_vslli_d_56(<16 x i8> %a) nounwind {186; CHECK-LABEL: shuffle_to_vslli_d_56:187; CHECK: # %bb.0:188; CHECK-NEXT: vslli.d $vr0, $vr0, 56189; CHECK-NEXT: ret190 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8>191 ret <16 x i8> %shuffle192}193 194define <16 x i8> @shuffle_to_vsrli_d_56(<16 x i8> %a) nounwind {195; CHECK-LABEL: shuffle_to_vsrli_d_56:196; CHECK: # %bb.0:197; CHECK-NEXT: vsrli.d $vr0, $vr0, 56198; CHECK-NEXT: ret199 %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>200 ret <16 x i8> %shuffle201}202