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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA644 5define void @shuffle_sign_ext_2i8_to_2i64(ptr %ptr, ptr %dst) nounwind {6; CHECK-LABEL: shuffle_sign_ext_2i8_to_2i64:7; CHECK: # %bb.0:8; CHECK-NEXT: ld.h $a0, $a0, 09; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 010; CHECK-NEXT: vrepli.b $vr1, 011; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr012; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr013; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr014; CHECK-NEXT: vst $vr0, $a1, 015; CHECK-NEXT: ret16 %x = load <2 x i8>, ptr %ptr17 %y = shufflevector <2 x i8> %x, <2 x i8> zeroinitializer, <16 x i32> <i32 0, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 1, i32 2, i32 2, i32 2,i32 2, i32 2, i32 2, i32 2>18 %r = bitcast <16 x i8> %y to <2 x i64>19 store <2 x i64> %r, ptr %dst20 ret void21}22 23define void @shuffle_sign_ext_2i16_to_2i64(ptr %ptr, ptr %dst) nounwind {24; CHECK-LABEL: shuffle_sign_ext_2i16_to_2i64:25; CHECK: # %bb.0:26; CHECK-NEXT: ld.w $a0, $a0, 027; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 028; CHECK-NEXT: vrepli.b $vr1, 029; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr030; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr031; CHECK-NEXT: vst $vr0, $a1, 032; CHECK-NEXT: ret33 %x = load <2 x i16>, ptr %ptr34 %y = shufflevector <2 x i16> %x, <2 x i16> zeroinitializer, <8 x i32> <i32 0, i32 3, i32 3, i32 3, i32 1, i32 2, i32 2, i32 2>35 %r = bitcast <8 x i16> %y to <2 x i64>36 store <2 x i64> %r, ptr %dst37 ret void38}39 40define void @shuffle_sign_ext_2i32_to_2i64(ptr %ptr, ptr %dst) nounwind {41; LA32-LABEL: shuffle_sign_ext_2i32_to_2i64:42; LA32: # %bb.0:43; LA32-NEXT: ld.w $a2, $a0, 044; LA32-NEXT: ld.w $a0, $a0, 445; LA32-NEXT: vrepli.b $vr0, 046; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 047; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 248; LA32-NEXT: vst $vr0, $a1, 049; LA32-NEXT: ret50;51; LA64-LABEL: shuffle_sign_ext_2i32_to_2i64:52; LA64: # %bb.0:53; LA64-NEXT: ld.d $a0, $a0, 054; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 055; LA64-NEXT: vrepli.b $vr1, 056; LA64-NEXT: vilvl.w $vr0, $vr1, $vr057; LA64-NEXT: vst $vr0, $a1, 058; LA64-NEXT: ret59 %x = load <2 x i32>, ptr %ptr60 %y = shufflevector <2 x i32> %x, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 3, i32 1, i32 2>61 %r = bitcast <4 x i32> %y to <2 x i64>62 store <2 x i64> %r, ptr %dst63 ret void64}65 66define void @shuffle_sign_ext_4i8_to_4i32(ptr %ptr, ptr %dst) nounwind {67; CHECK-LABEL: shuffle_sign_ext_4i8_to_4i32:68; CHECK: # %bb.0:69; CHECK-NEXT: ld.w $a0, $a0, 070; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 071; CHECK-NEXT: vrepli.b $vr1, 072; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr073; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr074; CHECK-NEXT: vst $vr0, $a1, 075; CHECK-NEXT: ret76 %x = load <4 x i8>, ptr %ptr77 %y = shufflevector <4 x i8> %x, <4 x i8> zeroinitializer, <16 x i32> <i32 0, i32 7, i32 7, i32 7, i32 1, i32 6, i32 6, i32 6, i32 2, i32 5, i32 5, i32 5, i32 3, i32 4, i32 4, i32 4>78 %r = bitcast <16 x i8> %y to <4 x i32>79 store <4 x i32> %r, ptr %dst80 ret void81}82 83define void @shuffle_sign_ext_4i16_to_4i32(ptr %ptr, ptr %dst) nounwind {84; LA32-LABEL: shuffle_sign_ext_4i16_to_4i32:85; LA32: # %bb.0:86; LA32-NEXT: ld.w $a2, $a0, 087; LA32-NEXT: ld.w $a0, $a0, 488; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 089; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 190; LA32-NEXT: vrepli.b $vr1, 091; LA32-NEXT: vilvl.h $vr0, $vr1, $vr092; LA32-NEXT: vst $vr0, $a1, 093; LA32-NEXT: ret94;95; LA64-LABEL: shuffle_sign_ext_4i16_to_4i32:96; LA64: # %bb.0:97; LA64-NEXT: ld.d $a0, $a0, 098; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 099; LA64-NEXT: vrepli.b $vr1, 0100; LA64-NEXT: vilvl.h $vr0, $vr1, $vr0101; LA64-NEXT: vst $vr0, $a1, 0102; LA64-NEXT: ret103 %x = load <4 x i16>, ptr %ptr104 %y = shufflevector <4 x i16> %x, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 7, i32 1, i32 6, i32 2, i32 5, i32 3, i32 4>105 %r = bitcast <8 x i16> %y to <4 x i32>106 store <4 x i32> %r, ptr %dst107 ret void108}109 110define void @shuffle_sign_ext_8i8_to_8i16(ptr %ptr, ptr %dst) nounwind {111; LA32-LABEL: shuffle_sign_ext_8i8_to_8i16:112; LA32: # %bb.0:113; LA32-NEXT: ld.w $a2, $a0, 0114; LA32-NEXT: ld.w $a0, $a0, 4115; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0116; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1117; LA32-NEXT: vrepli.b $vr1, 0118; LA32-NEXT: vilvl.b $vr0, $vr1, $vr0119; LA32-NEXT: vst $vr0, $a1, 0120; LA32-NEXT: ret121;122; LA64-LABEL: shuffle_sign_ext_8i8_to_8i16:123; LA64: # %bb.0:124; LA64-NEXT: ld.d $a0, $a0, 0125; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0126; LA64-NEXT: vrepli.b $vr1, 0127; LA64-NEXT: vilvl.b $vr0, $vr1, $vr0128; LA64-NEXT: vst $vr0, $a1, 0129; LA64-NEXT: ret130 %x = load <8 x i8>, ptr %ptr131 %y = shufflevector <8 x i8> %x, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 15, i32 1, i32 14, i32 2, i32 13, i32 3, i32 12, i32 4, i32 11, i32 5, i32 10, i32 6, i32 9, i32 7, i32 8>132 %r = bitcast <16 x i8> %y to <8 x i16>133 store <8 x i16> %r, ptr %dst134 ret void135}136 137define void @shuffle_sign_ext_4i32_to_4i64(ptr %ptr, ptr %dst) nounwind {138; CHECK-LABEL: shuffle_sign_ext_4i32_to_4i64:139; CHECK: # %bb.0:140; CHECK-NEXT: vld $vr0, $a0, 0141; CHECK-NEXT: vrepli.b $vr1, 0142; CHECK-NEXT: vilvl.w $vr2, $vr1, $vr0143; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0144; CHECK-NEXT: vst $vr0, $a1, 16145; CHECK-NEXT: vst $vr2, $a1, 0146; CHECK-NEXT: ret147 %x = load <4 x i32>, ptr %ptr148 %y = shufflevector <4 x i32> %x, <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 7, i32 1, i32 6, i32 2, i32 5, i32 3, i32 4>149 %r = bitcast <8 x i32> %y to <4 x i64>150 store <4 x i64> %r, ptr %dst151 ret void152}153 154define void @shuffle_sign_ext_8i16_to_8i32(ptr %ptr, ptr %dst) nounwind {155; CHECK-LABEL: shuffle_sign_ext_8i16_to_8i32:156; CHECK: # %bb.0:157; CHECK-NEXT: vld $vr0, $a0, 0158; CHECK-NEXT: vrepli.b $vr1, 0159; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr0160; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0161; CHECK-NEXT: vst $vr0, $a1, 16162; CHECK-NEXT: vst $vr2, $a1, 0163; CHECK-NEXT: ret164 %x = load <8 x i16>, ptr %ptr165 %y = shufflevector <8 x i16> %x, <8 x i16> zeroinitializer, <16 x i32> <i32 0, i32 15, i32 1, i32 14, i32 2, i32 13, i32 3, i32 12, i32 4, i32 11, i32 5, i32 10, i32 6, i32 9, i32 7, i32 8>166 %r = bitcast <16 x i16> %y to <8 x i32>167 store <8 x i32> %r, ptr %dst168 ret void169}170 171define void @shuffle_sign_ext_8i16_to_8i64(ptr %ptr, ptr %dst) nounwind {172; CHECK-LABEL: shuffle_sign_ext_8i16_to_8i64:173; CHECK: # %bb.0:174; CHECK-NEXT: vld $vr0, $a0, 0175; CHECK-NEXT: vrepli.b $vr1, 0176; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr0177; CHECK-NEXT: vilvl.w $vr3, $vr1, $vr2178; CHECK-NEXT: vilvh.w $vr2, $vr1, $vr2179; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0180; CHECK-NEXT: vilvl.w $vr4, $vr1, $vr0181; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0182; CHECK-NEXT: vst $vr0, $a1, 48183; CHECK-NEXT: vst $vr4, $a1, 32184; CHECK-NEXT: vst $vr2, $a1, 16185; CHECK-NEXT: vst $vr3, $a1, 0186; CHECK-NEXT: ret187 %x = load <8 x i16>, ptr %ptr188 %y = shufflevector <8 x i16> %x, <8 x i16> zeroinitializer, <32 x i32> <i32 0, i32 15, i32 15, i32 15, i32 1, i32 14, i32 14, i32 14, i32 2, i32 13, i32 13, i32 13, i32 3, i32 12, i32 12, i32 12, i32 4, i32 11, i32 11, i32 11, i32 5, i32 10, i32 10, i32 10, i32 6, i32 9, i32 9, i32 9, i32 7, i32 8, i32 8, i32 8>189 %r = bitcast <32 x i16> %y to <8 x i64>190 store <8 x i64> %r, ptr %dst191 ret void192}193 194define void @shuffle_sign_ext_16i8_to_16i16(ptr %ptr, ptr %dst) nounwind {195; CHECK-LABEL: shuffle_sign_ext_16i8_to_16i16:196; CHECK: # %bb.0:197; CHECK-NEXT: vld $vr0, $a0, 0198; CHECK-NEXT: vrepli.b $vr1, 0199; CHECK-NEXT: vilvl.b $vr2, $vr1, $vr0200; CHECK-NEXT: vilvh.b $vr0, $vr1, $vr0201; CHECK-NEXT: vst $vr0, $a1, 16202; CHECK-NEXT: vst $vr2, $a1, 0203; CHECK-NEXT: ret204 %x = load <16 x i8>, ptr %ptr205 %y = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <32 x i32> <i32 0, i32 31, i32 1, i32 30, i32 2, i32 29, i32 3, i32 28, i32 4, i32 27, i32 5, i32 26, i32 6, i32 25, i32 7, i32 24, i32 8, i32 23, i32 9, i32 22, i32 10, i32 21, i32 11, i32 20, i32 12, i32 19, i32 13, i32 18, i32 14, i32 17, i32 15, i32 16 >206 %r = bitcast <32 x i8> %y to <16 x i16>207 store <16 x i16> %r, ptr %dst208 ret void209}210 211define void @shuffle_sign_ext_16i8_to_16i32(ptr %ptr, ptr %dst) nounwind {212; CHECK-LABEL: shuffle_sign_ext_16i8_to_16i32:213; CHECK: # %bb.0:214; CHECK-NEXT: vld $vr0, $a0, 0215; CHECK-NEXT: vrepli.b $vr1, 0216; CHECK-NEXT: vilvl.b $vr2, $vr1, $vr0217; CHECK-NEXT: vilvl.h $vr3, $vr1, $vr2218; CHECK-NEXT: vilvh.h $vr2, $vr1, $vr2219; CHECK-NEXT: vilvh.b $vr0, $vr1, $vr0220; CHECK-NEXT: vilvl.h $vr4, $vr1, $vr0221; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0222; CHECK-NEXT: vst $vr0, $a1, 48223; CHECK-NEXT: vst $vr4, $a1, 32224; CHECK-NEXT: vst $vr2, $a1, 16225; CHECK-NEXT: vst $vr3, $a1, 0226; CHECK-NEXT: ret227 %x = load <16 x i8>, ptr %ptr228 %y = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <64 x i32> <i32 0, i32 31, i32 31, i32 31, i32 1, i32 30, i32 30, i32 30, i32 2, i32 29, i32 29, i32 29, i32 3, i32 28, i32 28, i32 28, i32 4, i32 27, i32 27, i32 27, i32 5, i32 26, i32 26, i32 26, i32 6, i32 25, i32 25, i32 25, i32 7, i32 24, i32 24, i32 24, i32 8, i32 23, i32 23, i32 23, i32 9, i32 22, i32 22, i32 22, i32 10, i32 21, i32 21, i32 21, i32 11, i32 20, i32 20, i32 20, i32 12, i32 19, i32 19, i32 19, i32 13, i32 18, i32 18, i32 18, i32 14, i32 17, i32 17, i32 17, i32 15, i32 16, i32 16, i32 16>229 %r = bitcast <64 x i8> %y to <16 x i32>230 store <16 x i32> %r, ptr %dst231 ret void232}233 234define void @shuffle_sign_ext_16i8_to_16i64(ptr %ptr, ptr %dst) nounwind {235; CHECK-LABEL: shuffle_sign_ext_16i8_to_16i64:236; CHECK: # %bb.0:237; CHECK-NEXT: vld $vr0, $a0, 0238; CHECK-NEXT: vrepli.b $vr1, 0239; CHECK-NEXT: vilvl.b $vr2, $vr1, $vr0240; CHECK-NEXT: vilvl.h $vr3, $vr1, $vr2241; CHECK-NEXT: vilvl.w $vr4, $vr1, $vr3242; CHECK-NEXT: vilvh.w $vr3, $vr1, $vr3243; CHECK-NEXT: vilvh.h $vr2, $vr1, $vr2244; CHECK-NEXT: vilvl.w $vr5, $vr1, $vr2245; CHECK-NEXT: vilvh.w $vr2, $vr1, $vr2246; CHECK-NEXT: vilvh.b $vr0, $vr1, $vr0247; CHECK-NEXT: vilvl.h $vr6, $vr1, $vr0248; CHECK-NEXT: vilvl.w $vr7, $vr1, $vr6249; CHECK-NEXT: vilvh.w $vr6, $vr1, $vr6250; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0251; CHECK-NEXT: vilvl.w $vr8, $vr1, $vr0252; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0253; CHECK-NEXT: vst $vr0, $a1, 112254; CHECK-NEXT: vst $vr8, $a1, 96255; CHECK-NEXT: vst $vr6, $a1, 80256; CHECK-NEXT: vst $vr7, $a1, 64257; CHECK-NEXT: vst $vr2, $a1, 48258; CHECK-NEXT: vst $vr5, $a1, 32259; CHECK-NEXT: vst $vr3, $a1, 16260; CHECK-NEXT: vst $vr4, $a1, 0261; CHECK-NEXT: ret262 %x = load <16 x i8>, ptr %ptr263 %y = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <128 x i32> <i32 0, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 1, i32 30, i32 30, i32 30, i32 30, i32 30, i32 30, i32 30, i32 2, i32 29, i32 29, i32 29, i32 29, i32 29, i32 29, i32 29, i32 3, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 4, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 5, i32 26, i32 26, i32 26, i32 26, i32 26, i32 26, i32 26, i32 6, i32 25, i32 25, i32 25, i32 25, i32 25, i32 25, i32 25, i32 7, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 8, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 9, i32 22, i32 22, i32 22, i32 22, i32 22, i32 22, i32 22, i32 10, i32 21, i32 21, i32 21, i32 21, i32 21, i32 21, i32 21, i32 11, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 12, i32 19, i32 19, i32 19, i32 19, i32 19, i32 19, i32 19, i32 13, i32 18, i32 18, i32 18, i32 18, i32 18, i32 18, i32 18, i32 14, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>264 %r = bitcast <128 x i8> %y to <16 x i64>265 store <16 x i64> %r, ptr %dst266 ret void267}268