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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA323; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA644 5 6define void @load_zext_2i8_to_2i64(ptr %ptr, ptr %dst) {7; CHECK-LABEL: load_zext_2i8_to_2i64:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: ld.h $a0, $a0, 010; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 011; CHECK-NEXT: vrepli.b $vr1, 012; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr013; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr014; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr015; CHECK-NEXT: vst $vr0, $a1, 016; CHECK-NEXT: ret17entry:18 %A = load <2 x i8>, ptr %ptr19 %B = zext <2 x i8> %A to <2 x i64>20 store <2 x i64> %B, ptr %dst21 ret void22}23 24define void @load_zext_4i8_to_4i32(ptr %ptr, ptr %dst) {25; CHECK-LABEL: load_zext_4i8_to_4i32:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: ld.w $a0, $a0, 028; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 029; CHECK-NEXT: vrepli.b $vr1, 030; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr031; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr032; CHECK-NEXT: vst $vr0, $a1, 033; CHECK-NEXT: ret34entry:35 %A = load <4 x i8>, ptr %ptr36 %B = zext <4 x i8> %A to <4 x i32>37 store <4 x i32> %B, ptr %dst38 ret void39}40 41define void @load_zext_8i8_to_8i16(ptr %ptr, ptr %dst) {42; LA32-LABEL: load_zext_8i8_to_8i16:43; LA32: # %bb.0: # %entry44; LA32-NEXT: ld.w $a2, $a0, 045; LA32-NEXT: ld.w $a0, $a0, 446; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 047; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 148; LA32-NEXT: vrepli.b $vr1, 049; LA32-NEXT: vilvl.b $vr0, $vr1, $vr050; LA32-NEXT: vst $vr0, $a1, 051; LA32-NEXT: ret52;53; LA64-LABEL: load_zext_8i8_to_8i16:54; LA64: # %bb.0: # %entry55; LA64-NEXT: ld.d $a0, $a0, 056; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 057; LA64-NEXT: vrepli.b $vr1, 058; LA64-NEXT: vilvl.b $vr0, $vr1, $vr059; LA64-NEXT: vst $vr0, $a1, 060; LA64-NEXT: ret61entry:62 %A = load <8 x i8>, ptr %ptr63 %B = zext <8 x i8> %A to <8 x i16>64 store <8 x i16> %B, ptr %dst65 ret void66}67 68define void @load_zext_2i16_to_2i64(ptr %ptr, ptr %dst) {69; CHECK-LABEL: load_zext_2i16_to_2i64:70; CHECK: # %bb.0: # %entry71; CHECK-NEXT: ld.w $a0, $a0, 072; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 073; CHECK-NEXT: vrepli.b $vr1, 074; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr075; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr076; CHECK-NEXT: vst $vr0, $a1, 077; CHECK-NEXT: ret78entry:79 %A = load <2 x i16>, ptr %ptr80 %B = zext <2 x i16> %A to <2 x i64>81 store <2 x i64> %B, ptr %dst82 ret void83}84 85define void @load_zext_4i16_to_4i32(ptr %ptr, ptr %dst) {86; LA32-LABEL: load_zext_4i16_to_4i32:87; LA32: # %bb.0: # %entry88; LA32-NEXT: ld.w $a2, $a0, 089; LA32-NEXT: ld.w $a0, $a0, 490; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 091; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 192; LA32-NEXT: vrepli.b $vr1, 093; LA32-NEXT: vilvl.h $vr0, $vr1, $vr094; LA32-NEXT: vst $vr0, $a1, 095; LA32-NEXT: ret96;97; LA64-LABEL: load_zext_4i16_to_4i32:98; LA64: # %bb.0: # %entry99; LA64-NEXT: ld.d $a0, $a0, 0100; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0101; LA64-NEXT: vrepli.b $vr1, 0102; LA64-NEXT: vilvl.h $vr0, $vr1, $vr0103; LA64-NEXT: vst $vr0, $a1, 0104; LA64-NEXT: ret105entry:106 %A = load <4 x i16>, ptr %ptr107 %B = zext <4 x i16> %A to <4 x i32>108 store <4 x i32> %B, ptr %dst109 ret void110}111 112define void @load_zext_2i32_to_2i64(ptr %ptr, ptr %dst) {113; LA32-LABEL: load_zext_2i32_to_2i64:114; LA32: # %bb.0: # %entry115; LA32-NEXT: ld.w $a2, $a0, 0116; LA32-NEXT: ld.w $a0, $a0, 4117; LA32-NEXT: vrepli.b $vr0, 0118; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0119; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2120; LA32-NEXT: vst $vr0, $a1, 0121; LA32-NEXT: ret122;123; LA64-LABEL: load_zext_2i32_to_2i64:124; LA64: # %bb.0: # %entry125; LA64-NEXT: ld.d $a0, $a0, 0126; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0127; LA64-NEXT: vrepli.b $vr1, 0128; LA64-NEXT: vilvl.w $vr0, $vr1, $vr0129; LA64-NEXT: vst $vr0, $a1, 0130; LA64-NEXT: ret131entry:132 %A = load <2 x i32>, ptr %ptr133 %B = zext <2 x i32> %A to <2 x i64>134 store <2 x i64> %B, ptr %dst135 ret void136}137 138define void @load_zext_16i8_to_16i16(ptr %ptr, ptr %dst) {139; CHECK-LABEL: load_zext_16i8_to_16i16:140; CHECK: # %bb.0: # %entry141; CHECK-NEXT: vld $vr0, $a0, 0142; CHECK-NEXT: vrepli.b $vr1, 0143; CHECK-NEXT: vilvl.b $vr2, $vr1, $vr0144; CHECK-NEXT: vilvh.b $vr0, $vr1, $vr0145; CHECK-NEXT: vst $vr0, $a1, 16146; CHECK-NEXT: vst $vr2, $a1, 0147; CHECK-NEXT: ret148entry:149 %A = load <16 x i8>, ptr %ptr150 %B = zext <16 x i8> %A to <16 x i16>151 store <16 x i16> %B, ptr %dst152 ret void153}154 155define void @load_zext_16i8_to_16i32(ptr %ptr, ptr %dst) {156; CHECK-LABEL: load_zext_16i8_to_16i32:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vld $vr0, $a0, 0159; CHECK-NEXT: vrepli.b $vr1, 0160; CHECK-NEXT: vilvl.b $vr2, $vr1, $vr0161; CHECK-NEXT: vilvl.h $vr3, $vr1, $vr2162; CHECK-NEXT: vilvh.h $vr2, $vr1, $vr2163; CHECK-NEXT: vilvh.b $vr0, $vr1, $vr0164; CHECK-NEXT: vilvl.h $vr4, $vr1, $vr0165; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0166; CHECK-NEXT: vst $vr0, $a1, 48167; CHECK-NEXT: vst $vr4, $a1, 32168; CHECK-NEXT: vst $vr2, $a1, 16169; CHECK-NEXT: vst $vr3, $a1, 0170; CHECK-NEXT: ret171entry:172 %A = load <16 x i8>, ptr %ptr173 %B = zext <16 x i8> %A to <16 x i32>174 store <16 x i32> %B, ptr %dst175 ret void176}177 178define void @load_zext_16i8_to_16i64(ptr %ptr, ptr %dst) {179; CHECK-LABEL: load_zext_16i8_to_16i64:180; CHECK: # %bb.0: # %entry181; CHECK-NEXT: vld $vr0, $a0, 0182; CHECK-NEXT: vrepli.b $vr1, 0183; CHECK-NEXT: vilvl.b $vr2, $vr1, $vr0184; CHECK-NEXT: vilvl.h $vr3, $vr1, $vr2185; CHECK-NEXT: vilvl.w $vr4, $vr1, $vr3186; CHECK-NEXT: vilvh.w $vr3, $vr1, $vr3187; CHECK-NEXT: vilvh.h $vr2, $vr1, $vr2188; CHECK-NEXT: vilvl.w $vr5, $vr1, $vr2189; CHECK-NEXT: vilvh.w $vr2, $vr1, $vr2190; CHECK-NEXT: vilvh.b $vr0, $vr1, $vr0191; CHECK-NEXT: vilvl.h $vr6, $vr1, $vr0192; CHECK-NEXT: vilvl.w $vr7, $vr1, $vr6193; CHECK-NEXT: vilvh.w $vr6, $vr1, $vr6194; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0195; CHECK-NEXT: vilvl.w $vr8, $vr1, $vr0196; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0197; CHECK-NEXT: vst $vr0, $a1, 112198; CHECK-NEXT: vst $vr8, $a1, 96199; CHECK-NEXT: vst $vr6, $a1, 80200; CHECK-NEXT: vst $vr7, $a1, 64201; CHECK-NEXT: vst $vr2, $a1, 48202; CHECK-NEXT: vst $vr5, $a1, 32203; CHECK-NEXT: vst $vr3, $a1, 16204; CHECK-NEXT: vst $vr4, $a1, 0205; CHECK-NEXT: ret206entry:207 %A = load <16 x i8>, ptr %ptr208 %B = zext <16 x i8> %A to <16 x i64>209 store <16 x i64> %B, ptr %dst210 ret void211}212 213define void @load_zext_8i16_to_8i32(ptr %ptr, ptr %dst) {214; CHECK-LABEL: load_zext_8i16_to_8i32:215; CHECK: # %bb.0: # %entry216; CHECK-NEXT: vld $vr0, $a0, 0217; CHECK-NEXT: vrepli.b $vr1, 0218; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr0219; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0220; CHECK-NEXT: vst $vr0, $a1, 16221; CHECK-NEXT: vst $vr2, $a1, 0222; CHECK-NEXT: ret223entry:224 %A = load <8 x i16>, ptr %ptr225 %B = zext <8 x i16> %A to <8 x i32>226 store <8 x i32> %B, ptr %dst227 ret void228}229 230define void @load_zext_8i16_to_8i64(ptr %ptr, ptr %dst) {231; CHECK-LABEL: load_zext_8i16_to_8i64:232; CHECK: # %bb.0: # %entry233; CHECK-NEXT: vld $vr0, $a0, 0234; CHECK-NEXT: vrepli.b $vr1, 0235; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr0236; CHECK-NEXT: vilvl.w $vr3, $vr1, $vr2237; CHECK-NEXT: vilvh.w $vr2, $vr1, $vr2238; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0239; CHECK-NEXT: vilvl.w $vr4, $vr1, $vr0240; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0241; CHECK-NEXT: vst $vr0, $a1, 48242; CHECK-NEXT: vst $vr4, $a1, 32243; CHECK-NEXT: vst $vr2, $a1, 16244; CHECK-NEXT: vst $vr3, $a1, 0245; CHECK-NEXT: ret246entry:247 %A = load <8 x i16>, ptr %ptr248 %B = zext <8 x i16> %A to <8 x i64>249 store <8 x i64> %B, ptr %dst250 ret void251}252 253define void @load_zext_4i32_to_4i64(ptr %ptr, ptr %dst) {254; CHECK-LABEL: load_zext_4i32_to_4i64:255; CHECK: # %bb.0: # %entry256; CHECK-NEXT: vld $vr0, $a0, 0257; CHECK-NEXT: vrepli.b $vr1, 0258; CHECK-NEXT: vilvl.w $vr2, $vr1, $vr0259; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0260; CHECK-NEXT: vst $vr0, $a1, 16261; CHECK-NEXT: vst $vr2, $a1, 0262; CHECK-NEXT: ret263entry:264 %A = load <4 x i32>, ptr %ptr265 %B = zext <4 x i32> %A to <4 x i64>266 store <4 x i64> %B, ptr %dst267 ret void268}269