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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s3; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s4 5define void @select_v16i8_imm(ptr %res, ptr %a0) nounwind {6; CHECK-LABEL: select_v16i8_imm:7; CHECK: # %bb.0:8; CHECK-NEXT: vld $vr0, $a1, 09; CHECK-NEXT: vrepli.h $vr1, -25610; CHECK-NEXT: vor.v $vr0, $vr0, $vr111; CHECK-NEXT: vst $vr0, $a0, 012; CHECK-NEXT: ret13 %v0 = load <16 x i8>, ptr %a014 %sel = select <16 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %v015 store <16 x i8> %sel, ptr %res16 ret void17}18 19define void @select_v16i8_imm_1(ptr %res, ptr %a0) nounwind {20; CHECK-LABEL: select_v16i8_imm_1:21; CHECK: # %bb.0:22; CHECK-NEXT: vld $vr0, $a1, 023; CHECK-NEXT: vrepli.h $vr1, -25624; CHECK-NEXT: vbitseli.b $vr1, $vr0, 125; CHECK-NEXT: vst $vr1, $a0, 026; CHECK-NEXT: ret27 %v0 = load <16 x i8>, ptr %a028 %sel = select <16 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8> %v029 store <16 x i8> %sel, ptr %res30 ret void31}32 33define void @select_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {34; CHECK-LABEL: select_v16i8:35; CHECK: # %bb.0:36; CHECK-NEXT: vld $vr0, $a1, 037; CHECK-NEXT: vld $vr1, $a2, 038; CHECK-NEXT: vrepli.h $vr2, -25639; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr240; CHECK-NEXT: vst $vr0, $a0, 041; CHECK-NEXT: ret42 %v0 = load <16 x i8>, ptr %a043 %v1 = load <16 x i8>, ptr %a144 %sel = select <16 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <16 x i8> %v0, <16 x i8> %v145 store <16 x i8> %sel, ptr %res46 ret void47}48 49define void @select_v16i8_1(ptr %res, ptr %a0, ptr %a1) nounwind {50; CHECK-LABEL: select_v16i8_1:51; CHECK: # %bb.0:52; CHECK-NEXT: vld $vr0, $a1, 053; CHECK-NEXT: vld $vr1, $a2, 054; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)55; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI3_0)56; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr257; CHECK-NEXT: vst $vr0, $a0, 058; CHECK-NEXT: ret59 %v0 = load <16 x i8>, ptr %a060 %v1 = load <16 x i8>, ptr %a161 %sel = select <16 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x i8> %v0, <16 x i8> %v162 store <16 x i8> %sel, ptr %res63 ret void64}65 66define void @select_v16i8_2(ptr %res, ptr %a0, ptr %a1) nounwind {67; CHECK-LABEL: select_v16i8_2:68; CHECK: # %bb.0:69; CHECK-NEXT: vld $vr0, $a1, 070; CHECK-NEXT: vld $vr1, $a2, 071; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI4_0)72; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI4_0)73; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr274; CHECK-NEXT: vst $vr0, $a0, 075; CHECK-NEXT: ret76 %v0 = load <16 x i8>, ptr %a077 %v1 = load <16 x i8>, ptr %a178 %sel = select <16 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false>, <16 x i8> %v0, <16 x i8> %v179 store <16 x i8> %sel, ptr %res80 ret void81}82 83define void @select_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {84; CHECK-LABEL: select_v8i16:85; CHECK: # %bb.0:86; CHECK-NEXT: vld $vr0, $a1, 087; CHECK-NEXT: vld $vr1, $a2, 088; CHECK-NEXT: lu12i.w $a1, -1689; CHECK-NEXT: vreplgr2vr.w $vr2, $a190; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr291; CHECK-NEXT: vst $vr0, $a0, 092; CHECK-NEXT: ret93 %v0 = load <8 x i16>, ptr %a094 %v1 = load <8 x i16>, ptr %a195 %sel = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i16> %v0, <8 x i16> %v196 store <8 x i16> %sel, ptr %res97 ret void98}99 100define void @select_v8i16_1(ptr %res, ptr %a0, ptr %a1) nounwind {101; CHECK-LABEL: select_v8i16_1:102; CHECK: # %bb.0:103; CHECK-NEXT: vld $vr0, $a1, 0104; CHECK-NEXT: vld $vr1, $a2, 0105; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI6_0)106; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI6_0)107; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2108; CHECK-NEXT: vst $vr0, $a0, 0109; CHECK-NEXT: ret110 %v0 = load <8 x i16>, ptr %a0111 %v1 = load <8 x i16>, ptr %a1112 %sel = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %v0, <8 x i16> %v1113 store <8 x i16> %sel, ptr %res114 ret void115}116 117define void @select_v8i16_2(ptr %res, ptr %a0, ptr %a1) nounwind {118; CHECK-LABEL: select_v8i16_2:119; CHECK: # %bb.0:120; CHECK-NEXT: vld $vr0, $a1, 0121; CHECK-NEXT: vld $vr1, $a2, 0122; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI7_0)123; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI7_0)124; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2125; CHECK-NEXT: vst $vr0, $a0, 0126; CHECK-NEXT: ret127 %v0 = load <8 x i16>, ptr %a0128 %v1 = load <8 x i16>, ptr %a1129 %sel = select <8 x i1> <i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %v0, <8 x i16> %v1130 store <8 x i16> %sel, ptr %res131 ret void132}133 134define void @select_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {135; CHECK-LABEL: select_v4i32:136; CHECK: # %bb.0:137; CHECK-NEXT: vld $vr0, $a1, 0138; CHECK-NEXT: vld $vr1, $a2, 0139; CHECK-NEXT: vldi $vr2, -1552140; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2141; CHECK-NEXT: vst $vr0, $a0, 0142; CHECK-NEXT: ret143 %v0 = load <4 x i32>, ptr %a0144 %v1 = load <4 x i32>, ptr %a1145 %sel = select <4 x i1> <i1 false, i1 true, i1 false, i1 true>, <4 x i32> %v0, <4 x i32> %v1146 store <4 x i32> %sel, ptr %res147 ret void148}149 150define void @select_v4i32_1(ptr %res, ptr %a0, ptr %a1) nounwind {151; CHECK-LABEL: select_v4i32_1:152; CHECK: # %bb.0:153; CHECK-NEXT: vld $vr0, $a1, 0154; CHECK-NEXT: vld $vr1, $a2, 0155; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)156; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI9_0)157; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2158; CHECK-NEXT: vst $vr0, $a0, 0159; CHECK-NEXT: ret160 %v0 = load <4 x i32>, ptr %a0161 %v1 = load <4 x i32>, ptr %a1162 %sel = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i32> %v0, <4 x i32> %v1163 store <4 x i32> %sel, ptr %res164 ret void165}166 167define void @select_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {168; CHECK-LABEL: select_v4f32:169; CHECK: # %bb.0:170; CHECK-NEXT: vld $vr0, $a1, 0171; CHECK-NEXT: vld $vr1, $a2, 0172; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI10_0)173; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI10_0)174; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2175; CHECK-NEXT: vst $vr0, $a0, 0176; CHECK-NEXT: ret177 %v0 = load <4 x float>, ptr %a0178 %v1 = load <4 x float>, ptr %a1179 %sel = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %v0, <4 x float> %v1180 store <4 x float> %sel, ptr %res181 ret void182}183 184define void @select_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {185; CHECK-LABEL: select_v2i64:186; CHECK: # %bb.0:187; CHECK-NEXT: vld $vr0, $a1, 0188; CHECK-NEXT: vld $vr1, $a2, 0189; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)190; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI11_0)191; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2192; CHECK-NEXT: vst $vr0, $a0, 0193; CHECK-NEXT: ret194 %v0 = load <2 x i64>, ptr %a0195 %v1 = load <2 x i64>, ptr %a1196 %sel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v0, <2 x i64> %v1197 store <2 x i64> %sel, ptr %res198 ret void199}200 201define void @select_v2f64(ptr %res, ptr %a0, ptr %a1) nounwind {202; CHECK-LABEL: select_v2f64:203; CHECK: # %bb.0:204; CHECK-NEXT: vld $vr0, $a1, 0205; CHECK-NEXT: vld $vr1, $a2, 0206; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0)207; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI12_0)208; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2209; CHECK-NEXT: vst $vr0, $a0, 0210; CHECK-NEXT: ret211 %v0 = load <2 x double>, ptr %a0212 %v1 = load <2 x double>, ptr %a1213 %sel = select <2 x i1> <i1 false, i1 true>, <2 x double> %v0, <2 x double> %v1214 store <2 x double> %sel, ptr %res215 ret void216}217