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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc --mtriple=loongarch32 -mattr=+d < %s | FileCheck %s --check-prefix=LA323; RUN: llc --mtriple=loongarch64 -mattr=+d < %s | FileCheck %s --check-prefix=LA644 5;; This test checks that unnecessary masking of shift amount operands is6;; eliminated during instruction selection. The test needs to ensure that the7;; masking is not removed if it may affect the shift amount.8 9define i32 @sll_redundant_mask(i32 %a, i32 %b) {10; LA32-LABEL: sll_redundant_mask:11; LA32: # %bb.0:12; LA32-NEXT: sll.w $a0, $a0, $a113; LA32-NEXT: ret14;15; LA64-LABEL: sll_redundant_mask:16; LA64: # %bb.0:17; LA64-NEXT: sll.w $a0, $a0, $a118; LA64-NEXT: ret19 %1 = and i32 %b, 3120 %2 = shl i32 %a, %121 ret i32 %222}23 24define i32 @sll_non_redundant_mask(i32 %a, i32 %b) {25; LA32-LABEL: sll_non_redundant_mask:26; LA32: # %bb.0:27; LA32-NEXT: andi $a1, $a1, 1528; LA32-NEXT: sll.w $a0, $a0, $a129; LA32-NEXT: ret30;31; LA64-LABEL: sll_non_redundant_mask:32; LA64: # %bb.0:33; LA64-NEXT: andi $a1, $a1, 1534; LA64-NEXT: sll.w $a0, $a0, $a135; LA64-NEXT: ret36 %1 = and i32 %b, 1537 %2 = shl i32 %a, %138 ret i32 %239}40 41define i32 @srl_redundant_mask(i32 %a, i32 %b) {42; LA32-LABEL: srl_redundant_mask:43; LA32: # %bb.0:44; LA32-NEXT: srl.w $a0, $a0, $a145; LA32-NEXT: ret46;47; LA64-LABEL: srl_redundant_mask:48; LA64: # %bb.0:49; LA64-NEXT: srl.w $a0, $a0, $a150; LA64-NEXT: ret51 %1 = and i32 %b, 409552 %2 = lshr i32 %a, %153 ret i32 %254}55 56define i32 @srl_non_redundant_mask(i32 %a, i32 %b) {57; LA32-LABEL: srl_non_redundant_mask:58; LA32: # %bb.0:59; LA32-NEXT: andi $a1, $a1, 760; LA32-NEXT: srl.w $a0, $a0, $a161; LA32-NEXT: ret62;63; LA64-LABEL: srl_non_redundant_mask:64; LA64: # %bb.0:65; LA64-NEXT: andi $a1, $a1, 766; LA64-NEXT: srl.w $a0, $a0, $a167; LA64-NEXT: ret68 %1 = and i32 %b, 769 %2 = lshr i32 %a, %170 ret i32 %271}72 73define i32 @sra_redundant_mask(i32 %a, i32 %b) {74; LA32-LABEL: sra_redundant_mask:75; LA32: # %bb.0:76; LA32-NEXT: sra.w $a0, $a0, $a177; LA32-NEXT: ret78;79; LA64-LABEL: sra_redundant_mask:80; LA64: # %bb.0:81; LA64-NEXT: sra.w $a0, $a0, $a182; LA64-NEXT: ret83 %1 = and i32 %b, 6553584 %2 = ashr i32 %a, %185 ret i32 %286}87 88define i32 @sra_non_redundant_mask(i32 %a, i32 %b) {89; LA32-LABEL: sra_non_redundant_mask:90; LA32: # %bb.0:91; LA32-NEXT: andi $a1, $a1, 3292; LA32-NEXT: sra.w $a0, $a0, $a193; LA32-NEXT: ret94;95; LA64-LABEL: sra_non_redundant_mask:96; LA64: # %bb.0:97; LA64-NEXT: andi $a1, $a1, 3298; LA64-NEXT: sra.w $a0, $a0, $a199; LA64-NEXT: ret100 %1 = and i32 %b, 32101 %2 = ashr i32 %a, %1102 ret i32 %2103}104 105define i32 @sll_redundant_mask_zeros(i32 %a, i32 %b) {106; LA32-LABEL: sll_redundant_mask_zeros:107; LA32: # %bb.0:108; LA32-NEXT: slli.w $a1, $a1, 1109; LA32-NEXT: sll.w $a0, $a0, $a1110; LA32-NEXT: ret111;112; LA64-LABEL: sll_redundant_mask_zeros:113; LA64: # %bb.0:114; LA64-NEXT: slli.d $a1, $a1, 1115; LA64-NEXT: sll.w $a0, $a0, $a1116; LA64-NEXT: ret117 %1 = shl i32 %b, 1118 %2 = and i32 %1, 30119 %3 = shl i32 %a, %2120 ret i32 %3121}122 123define i32 @srl_redundant_mask_zeros(i32 %a, i32 %b) {124; LA32-LABEL: srl_redundant_mask_zeros:125; LA32: # %bb.0:126; LA32-NEXT: slli.w $a1, $a1, 2127; LA32-NEXT: srl.w $a0, $a0, $a1128; LA32-NEXT: ret129;130; LA64-LABEL: srl_redundant_mask_zeros:131; LA64: # %bb.0:132; LA64-NEXT: slli.d $a1, $a1, 2133; LA64-NEXT: srl.w $a0, $a0, $a1134; LA64-NEXT: ret135 %1 = shl i32 %b, 2136 %2 = and i32 %1, 28137 %3 = lshr i32 %a, %2138 ret i32 %3139}140 141define i32 @sra_redundant_mask_zeros(i32 %a, i32 %b) {142; LA32-LABEL: sra_redundant_mask_zeros:143; LA32: # %bb.0:144; LA32-NEXT: slli.w $a1, $a1, 3145; LA32-NEXT: sra.w $a0, $a0, $a1146; LA32-NEXT: ret147;148; LA64-LABEL: sra_redundant_mask_zeros:149; LA64: # %bb.0:150; LA64-NEXT: slli.d $a1, $a1, 3151; LA64-NEXT: sra.w $a0, $a0, $a1152; LA64-NEXT: ret153 %1 = shl i32 %b, 3154 %2 = and i32 %1, 24155 %3 = ashr i32 %a, %2156 ret i32 %3157}158 159define i64 @sll_redundant_mask_zeros_i64(i64 %a, i64 %b) {160; LA32-LABEL: sll_redundant_mask_zeros_i64:161; LA32: # %bb.0:162; LA32-NEXT: slli.w $a2, $a2, 2163; LA32-NEXT: andi $a4, $a2, 60164; LA32-NEXT: addi.w $a3, $a4, -32165; LA32-NEXT: bltz $a3, .LBB9_2166; LA32-NEXT: # %bb.1:167; LA32-NEXT: sll.w $a1, $a0, $a3168; LA32-NEXT: b .LBB9_3169; LA32-NEXT: .LBB9_2:170; LA32-NEXT: sll.w $a1, $a1, $a2171; LA32-NEXT: srli.w $a5, $a0, 1172; LA32-NEXT: xori $a4, $a4, 31173; LA32-NEXT: srl.w $a4, $a5, $a4174; LA32-NEXT: or $a1, $a1, $a4175; LA32-NEXT: .LBB9_3:176; LA32-NEXT: slti $a3, $a3, 0177; LA32-NEXT: sub.w $a3, $zero, $a3178; LA32-NEXT: sll.w $a0, $a0, $a2179; LA32-NEXT: and $a0, $a3, $a0180; LA32-NEXT: ret181;182; LA64-LABEL: sll_redundant_mask_zeros_i64:183; LA64: # %bb.0:184; LA64-NEXT: slli.d $a1, $a1, 2185; LA64-NEXT: sll.d $a0, $a0, $a1186; LA64-NEXT: ret187 %1 = shl i64 %b, 2188 %2 = and i64 %1, 60189 %3 = shl i64 %a, %2190 ret i64 %3191}192 193define i64 @srl_redundant_mask_zeros_i64(i64 %a, i64 %b) {194; LA32-LABEL: srl_redundant_mask_zeros_i64:195; LA32: # %bb.0:196; LA32-NEXT: slli.w $a2, $a2, 3197; LA32-NEXT: andi $a4, $a2, 56198; LA32-NEXT: addi.w $a3, $a4, -32199; LA32-NEXT: bltz $a3, .LBB10_2200; LA32-NEXT: # %bb.1:201; LA32-NEXT: srl.w $a0, $a1, $a3202; LA32-NEXT: b .LBB10_3203; LA32-NEXT: .LBB10_2:204; LA32-NEXT: srl.w $a0, $a0, $a2205; LA32-NEXT: slli.w $a5, $a1, 1206; LA32-NEXT: xori $a4, $a4, 31207; LA32-NEXT: sll.w $a4, $a5, $a4208; LA32-NEXT: or $a0, $a0, $a4209; LA32-NEXT: .LBB10_3:210; LA32-NEXT: slti $a3, $a3, 0211; LA32-NEXT: sub.w $a3, $zero, $a3212; LA32-NEXT: srl.w $a1, $a1, $a2213; LA32-NEXT: and $a1, $a3, $a1214; LA32-NEXT: ret215;216; LA64-LABEL: srl_redundant_mask_zeros_i64:217; LA64: # %bb.0:218; LA64-NEXT: slli.d $a1, $a1, 3219; LA64-NEXT: srl.d $a0, $a0, $a1220; LA64-NEXT: ret221 %1 = shl i64 %b, 3222 %2 = and i64 %1, 56223 %3 = lshr i64 %a, %2224 ret i64 %3225}226 227define i64 @sra_redundant_mask_zeros_i64(i64 %a, i64 %b) {228; LA32-LABEL: sra_redundant_mask_zeros_i64:229; LA32: # %bb.0:230; LA32-NEXT: slli.w $a2, $a2, 4231; LA32-NEXT: andi $a3, $a2, 48232; LA32-NEXT: addi.w $a4, $a3, -32233; LA32-NEXT: bltz $a4, .LBB11_2234; LA32-NEXT: # %bb.1:235; LA32-NEXT: sra.w $a0, $a1, $a4236; LA32-NEXT: srai.w $a1, $a1, 31237; LA32-NEXT: ret238; LA32-NEXT: .LBB11_2:239; LA32-NEXT: srl.w $a0, $a0, $a2240; LA32-NEXT: slli.w $a4, $a1, 1241; LA32-NEXT: xori $a3, $a3, 31242; LA32-NEXT: sll.w $a3, $a4, $a3243; LA32-NEXT: or $a0, $a0, $a3244; LA32-NEXT: sra.w $a1, $a1, $a2245; LA32-NEXT: ret246;247; LA64-LABEL: sra_redundant_mask_zeros_i64:248; LA64: # %bb.0:249; LA64-NEXT: slli.d $a1, $a1, 4250; LA64-NEXT: sra.d $a0, $a0, $a1251; LA64-NEXT: ret252 %1 = shl i64 %b, 4253 %2 = and i64 %1, 48254 %3 = ashr i64 %a, %2255 ret i64 %3256}257