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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=m68k -verify-machineinstrs | FileCheck %s3 4define zeroext i8 @umul_i8(i8 signext %a, i8 signext %b) nounwind ssp {5; CHECK-LABEL: umul_i8:6; CHECK: ; %bb.0: ; %entry7; CHECK-NEXT: move.b (11,%sp), %d08; CHECK-NEXT: and.l #255, %d09; CHECK-NEXT: move.b (7,%sp), %d110; CHECK-NEXT: and.l #255, %d111; CHECK-NEXT: muls %d0, %d112; CHECK-NEXT: move.l %d1, %d013; CHECK-NEXT: and.l #65535, %d014; CHECK-NEXT: and.l #255, %d015; CHECK-NEXT: rts16entry:17 %umul = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %a, i8 %b)18 %cmp = extractvalue { i8, i1 } %umul, 119 %umul.result = extractvalue { i8, i1 } %umul, 020 %X = select i1 %cmp, i8 42, i8 %umul.result21 ret i8 %X22}23 24define zeroext i8 @umul_i8_no_ovf(i8 signext %a, i8 signext %b) nounwind ssp {25; CHECK-LABEL: umul_i8_no_ovf:26; CHECK: ; %bb.0: ; %entry27; CHECK-NEXT: moveq #42, %d028; CHECK-NEXT: rts29entry:30 %umul = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %a, i8 %b)31 %cmp = extractvalue { i8, i1 } %umul, 132 %umul.result = extractvalue { i8, i1 } %umul, 033 %X = select i1 %cmp, i8 %umul.result, i8 4234 ret i8 %X35}36 37declare { i8, i1 } @llvm.umul.with.overflow.i8(i8, i8) nounwind readnone38 39define zeroext i16 @umul_i16(i16 signext %a, i16 signext %b) nounwind ssp {40; CHECK-LABEL: umul_i16:41; CHECK: ; %bb.0: ; %entry42; CHECK-NEXT: move.w (6,%sp), %d043; CHECK-NEXT: move.w (10,%sp), %d144; CHECK-NEXT: muls %d1, %d045; CHECK-NEXT: and.l #65535, %d046; CHECK-NEXT: rts47entry:48 %umul = tail call { i16, i1 } @llvm.umul.with.overflow.i16(i16 %a, i16 %b)49 %cmp = extractvalue { i16, i1 } %umul, 150 %umul.result = extractvalue { i16, i1 } %umul, 051 %X = select i1 %cmp, i16 42, i16 %umul.result52 ret i16 %X53}54 55declare { i16, i1 } @llvm.umul.with.overflow.i16(i16, i16) nounwind readnone56 57declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b)58 59define i1 @a(i32 %x) nounwind {60; CHECK-LABEL: a:61; CHECK: ; %bb.0:62; CHECK-NEXT: moveq #3, %d063; CHECK-NEXT: move.l (4,%sp), %d164; CHECK-NEXT: mulu.l %d0, %d165; CHECK-NEXT: svs %d066; CHECK-NEXT: rts67 %res = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 3)68 %obil = extractvalue {i32, i1} %res, 169 ret i1 %obil70}71 72define i32 @test2(i32 %a, i32 %b) nounwind readnone {73; CHECK-LABEL: test2:74; CHECK: ; %bb.0: ; %entry75; CHECK-NEXT: move.l (8,%sp), %d076; CHECK-NEXT: add.l (4,%sp), %d077; CHECK-NEXT: add.l %d0, %d078; CHECK-NEXT: rts79entry:80 %tmp0 = add i32 %b, %a81 %tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 2)82 %tmp2 = extractvalue { i32, i1 } %tmp1, 083 ret i32 %tmp284}85 86; It shouldn't fallback to builtin in this scenario87; Since we don't need the overflow bit here88define i32 @test3(i32 %a, i32 %b) nounwind readnone {89; CHECK-LABEL: test3:90; CHECK: ; %bb.0: ; %entry91; CHECK-NEXT: move.l (8,%sp), %d092; CHECK-NEXT: add.l (4,%sp), %d093; CHECK-NEXT: moveq #4, %d194; CHECK-NEXT: mulu.l %d1, %d095; CHECK-NEXT: rts96entry:97 %tmp0 = add i32 %b, %a98 %tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 4)99 %tmp2 = extractvalue { i32, i1 } %tmp1, 0100 ret i32 %tmp2101}102