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1; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs %s -o - | FileCheck %s2 3; Test that long branch reserved register is serialized through4; MIR.5 6; CHECK-LABEL: {{^}}name: uniform_long_forward_branch7; CHECK: machineFunctionInfo:8; CHECK-NEXT: explicitKernArgSize: 129; CHECK-NEXT: maxKernArgAlign: 810; CHECK-NEXT: ldsSize: 011; CHECK-NEXT: gdsSize: 012; CHECK-NEXT: dynLDSAlign: 113; CHECK-NEXT: isEntryFunction: true14; CHECK-NEXT: isChainFunction: false15; CHECK-NEXT: noSignedZerosFPMath: false16; CHECK-NEXT: memoryBound: false17; CHECK-NEXT: waveLimiter: false18; CHECK-NEXT: hasSpilledSGPRs: false19; CHECK-NEXT: hasSpilledVGPRs: false20; CHECK-NEXT: numWaveDispatchSGPRs: 021; CHECK-NEXT: numWaveDispatchVGPRs: 022; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'23; CHECK-NEXT: frameOffsetReg: '$fp_reg'24; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'25; CHECK-NEXT: bytesInStackArgArea: 026; CHECK-NEXT: returnsVoid: true27; CHECK-NEXT: argumentInfo:28; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }29; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }30; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' }31; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }32; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }33; CHECK-NEXT: psInputAddr: 034; CHECK-NEXT: psInputEnable: 035; CHECK-NEXT: maxMemoryClusterDWords: 836; CHECK-NEXT: mode:37; CHECK-NEXT: ieee: true38; CHECK-NEXT: dx10-clamp: true39; CHECK-NEXT: fp32-input-denormals: true40; CHECK-NEXT: fp32-output-denormals: true41; CHECK-NEXT: fp64-fp16-input-denormals: true42; CHECK-NEXT: fp64-fp16-output-denormals: true43; CHECK-NEXT: BitsOf32BitAddress: 044; CHECK-NEXT: occupancy: 1045; CHECK-NEXT: vgprForAGPRCopy: ''46; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'47; CHECK-NEXT: longBranchReservedReg: '$sgpr2_sgpr3'48; CHECK-NEXT: hasInitWholeWave: false49; CHECK-NEXT: dynamicVGPRBlockSize: 050; CHECK-NEXT: scratchReservedForDynamicVGPRs: 051; CHECK-NEXT: numKernargPreloadSGPRs: 052; CHECK-NEXT: isWholeWaveFunction: false53; CHECK-NEXT: body:54define amdgpu_kernel void @uniform_long_forward_branch(ptr addrspace(1) %arg, i32 %arg1) #0 {55bb0:56 %tmp = icmp ne i32 %arg1, 057 br i1 %tmp, label %bb2, label %bb358 59bb2:60 store volatile i32 17, ptr addrspace(1) poison61 br label %bb462 63bb3:64 ; 32 byte asm65 call void asm sideeffect66 "v_nop_e6467 v_nop_e6468 v_nop_e6469 v_nop_e64", ""() #070 br label %bb471 72bb4:73 store volatile i32 63, ptr addrspace(1) %arg74 ret void75}76 77attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }78attributes #1 = { nounwind readnone }79