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1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=si-pre-allocate-wwm-regs -o %t.mir %s2; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s3 4; Test that SIMachineFunctionInfo can be round trip serialized through5; MIR.6 7@lds = addrspace(3) global [512 x float] undef, align 48 9; CHECK-LABEL: {{^}}name: kernel10; CHECK: machineFunctionInfo:11; CHECK-NEXT: explicitKernArgSize: 12812; CHECK-NEXT: maxKernArgAlign: 6413; CHECK-NEXT: ldsSize: 204814; CHECK-NEXT: gdsSize: 015; CHECK-NEXT: dynLDSAlign: 116; CHECK-NEXT: isEntryFunction: true17; CHECK-NEXT: isChainFunction: false18; CHECK-NEXT: noSignedZerosFPMath: false19; CHECK-NEXT: memoryBound: false20; CHECK-NEXT: waveLimiter: false21; CHECK-NEXT: hasSpilledSGPRs: false22; CHECK-NEXT: hasSpilledVGPRs: false23; CHECK-NEXT: numWaveDispatchSGPRs: 024; CHECK-NEXT: numWaveDispatchVGPRs: 025; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'26; CHECK-NEXT: frameOffsetReg: '$fp_reg'27; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'28; CHECK-NEXT: bytesInStackArgArea: 029; CHECK-NEXT: returnsVoid: true30; CHECK-NEXT: argumentInfo:31; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }32; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }33; CHECK-NEXT: queuePtr: { reg: '$sgpr6_sgpr7' }34; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr8_sgpr9' }35; CHECK-NEXT: dispatchID: { reg: '$sgpr10_sgpr11' }36; CHECK-NEXT: workGroupIDX: { reg: '$sgpr12' }37; CHECK-NEXT: workGroupIDY: { reg: '$sgpr13' }38; CHECK-NEXT: workGroupIDZ: { reg: '$sgpr14' }39; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr15' }40; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }41; CHECK-NEXT: workItemIDY: { reg: '$vgpr1' }42; CHECK-NEXT: workItemIDZ: { reg: '$vgpr2' }43; CHECK-NEXT: psInputAddr: 044; CHECK-NEXT: psInputEnable: 045; CHECK-NEXT: maxMemoryClusterDWords: 846; CHECK-NEXT: mode:47; CHECK-NEXT: ieee: true48; CHECK-NEXT: dx10-clamp: true49; CHECK-NEXT: fp32-input-denormals: true50; CHECK-NEXT: fp32-output-denormals: true51; CHECK-NEXT: fp64-fp16-input-denormals: true52; CHECK-NEXT: fp64-fp16-output-denormals: true53; CHECK-NEXT: highBitsOf32BitAddress: 054; CHECK-NEXT: occupancy: 855; CHECK-NEXT: vgprForAGPRCopy: ''56; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'57; CHECK-NEXT: longBranchReservedReg: ''58; CHECK-NEXT: hasInitWholeWave: false59; CHECK-NEXT: dynamicVGPRBlockSize: 060; CHECK-NEXT: scratchReservedForDynamicVGPRs: 061; CHECK-NEXT: numKernargPreloadSGPRs: 062; CHECK-NEXT: isWholeWaveFunction: false63; CHECK-NEXT: body:64define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {65 %gep = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %arg066 store float 0.0, ptr addrspace(3) %gep, align 467 ret void68}69 70@gds = addrspace(2) global [128 x i32] undef, align 471 72; CHECK-LABEL: {{^}}name: ps_shader73; CHECK: machineFunctionInfo:74; CHECK-NEXT: explicitKernArgSize: 075; CHECK-NEXT: maxKernArgAlign: 476; CHECK-NEXT: ldsSize: 077; CHECK-NEXT: gdsSize: 51278; CHECK-NEXT: dynLDSAlign: 179; CHECK-NEXT: isEntryFunction: true80; CHECK-NEXT: isChainFunction: false81; CHECK-NEXT: noSignedZerosFPMath: false82; CHECK-NEXT: memoryBound: false83; CHECK-NEXT: waveLimiter: false84; CHECK-NEXT: hasSpilledSGPRs: false85; CHECK-NEXT: hasSpilledVGPRs: false86; CHECK-NEXT: numWaveDispatchSGPRs: 387; CHECK-NEXT: numWaveDispatchVGPRs: 188; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'89; CHECK-NEXT: frameOffsetReg: '$fp_reg'90; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'91; CHECK-NEXT: bytesInStackArgArea: 092; CHECK-NEXT: returnsVoid: true93; CHECK-NEXT: argumentInfo:94; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' }95; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' }96; CHECK-NEXT: psInputAddr: 197; CHECK-NEXT: psInputEnable: 198; CHECK-NEXT: maxMemoryClusterDWords: 899; CHECK-NEXT: mode:100; CHECK-NEXT: ieee: false101; CHECK-NEXT: dx10-clamp: true102; CHECK-NEXT: fp32-input-denormals: true103; CHECK-NEXT: fp32-output-denormals: true104; CHECK-NEXT: fp64-fp16-input-denormals: true105; CHECK-NEXT: fp64-fp16-output-denormals: true106; CHECK-NEXT: highBitsOf32BitAddress: 0107; CHECK-NEXT: occupancy: 10108; CHECK-NEXT: vgprForAGPRCopy: ''109; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'110; CHECK-NEXT: longBranchReservedReg: ''111; CHECK-NEXT: hasInitWholeWave: false112; CHECK-NEXT: dynamicVGPRBlockSize: 0113; CHECK-NEXT: scratchReservedForDynamicVGPRs: 0114; CHECK-NEXT: numKernargPreloadSGPRs: 0115; CHECK-NEXT: isWholeWaveFunction: false116; CHECK-NEXT: body:117define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {118 %gep = getelementptr inbounds [128 x i32], ptr addrspace(2) @gds, i32 0, i32 %arg0119 atomicrmw add ptr addrspace(2) %gep, i32 8 seq_cst120 ret void121}122 123; CHECK-LABEL: {{^}}name: ps_shader_ps_input_enable124; CHECK: machineFunctionInfo:125; CHECK: psInputAddr: 36983126; CHECK-NEXT: psInputEnable: 1{{$}}127define amdgpu_ps void @ps_shader_ps_input_enable(i32 %arg0, i32 inreg %arg1) #7 {128 %gep = getelementptr inbounds [128 x i32], ptr addrspace(2) @gds, i32 0, i32 %arg0129 atomicrmw add ptr addrspace(2) %gep, i32 8 seq_cst130 ret void131}132 133; CHECK-LABEL: {{^}}name: gds_size_shader134; CHECK: gdsSize: 4096135define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 {136 ret void137}138 139; CHECK-LABEL: {{^}}name: function140; CHECK: machineFunctionInfo:141; CHECK-NEXT: explicitKernArgSize: 0142; CHECK-NEXT: maxKernArgAlign: 1143; CHECK-NEXT: ldsSize: 0144; CHECK-NEXT: gdsSize: 0145; CHECK-NEXT: dynLDSAlign: 1146; CHECK-NEXT: isEntryFunction: false147; CHECK-NEXT: isChainFunction: false148; CHECK-NEXT: noSignedZerosFPMath: false149; CHECK-NEXT: memoryBound: false150; CHECK-NEXT: waveLimiter: false151; CHECK-NEXT: hasSpilledSGPRs: false152; CHECK-NEXT: hasSpilledVGPRs: false153; CHECK-NEXT: numWaveDispatchSGPRs: 16154; CHECK-NEXT: numWaveDispatchVGPRs: 0155; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'156; CHECK-NEXT: frameOffsetReg: '$sgpr33'157; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'158; CHECK-NEXT: bytesInStackArgArea: 0159; CHECK-NEXT: returnsVoid: true160; CHECK-NEXT: argumentInfo:161; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }162; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }163; CHECK-NEXT: queuePtr: { reg: '$sgpr6_sgpr7' }164; CHECK-NEXT: dispatchID: { reg: '$sgpr10_sgpr11' }165; CHECK-NEXT: workGroupIDX: { reg: '$sgpr12' }166; CHECK-NEXT: workGroupIDY: { reg: '$sgpr13' }167; CHECK-NEXT: workGroupIDZ: { reg: '$sgpr14' }168; CHECK-NEXT: LDSKernelId: { reg: '$sgpr15' }169; CHECK-NEXT: implicitArgPtr: { reg: '$sgpr8_sgpr9' }170; CHECK-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 }171; CHECK-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 }172; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 }173; CHECK-NEXT: psInputAddr: 0174; CHECK-NEXT: psInputEnable: 0175; CHECK-NEXT: maxMemoryClusterDWords: 8176; CHECK-NEXT: mode:177; CHECK-NEXT: ieee: true178; CHECK-NEXT: dx10-clamp: true179; CHECK-NEXT: fp32-input-denormals: true180; CHECK-NEXT: fp32-output-denormals: true181; CHECK-NEXT: fp64-fp16-input-denormals: true182; CHECK-NEXT: fp64-fp16-output-denormals: true183; CHECK-NEXT: highBitsOf32BitAddress: 0184; CHECK-NEXT: occupancy: 10185; CHECK-NEXT: vgprForAGPRCopy: ''186; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'187; CHECK-NEXT: longBranchReservedReg: ''188; CHECK-NEXT: hasInitWholeWave: false189; CHECK-NEXT: dynamicVGPRBlockSize: 0190; CHECK-NEXT: scratchReservedForDynamicVGPRs: 0191; CHECK-NEXT: numKernargPreloadSGPRs: 0192; CHECK-NEXT: isWholeWaveFunction: false193; CHECK-NEXT: body:194define void @function() {195 ret void196}197 198; CHECK-LABEL: {{^}}name: function_nsz199; CHECK: machineFunctionInfo:200; CHECK-NEXT: explicitKernArgSize: 0201; CHECK-NEXT: maxKernArgAlign: 1202; CHECK-NEXT: ldsSize: 0203; CHECK-NEXT: gdsSize: 0204; CHECK-NEXT: dynLDSAlign: 1205; CHECK-NEXT: isEntryFunction: false206; CHECK-NEXT: isChainFunction: false207; CHECK-NEXT: noSignedZerosFPMath: true208; CHECK-NEXT: memoryBound: false209; CHECK-NEXT: waveLimiter: false210; CHECK-NEXT: hasSpilledSGPRs: false211; CHECK-NEXT: hasSpilledVGPRs: false212; CHECK-NEXT: numWaveDispatchSGPRs: 16213; CHECK-NEXT: numWaveDispatchVGPRs: 0214; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'215; CHECK-NEXT: frameOffsetReg: '$sgpr33'216; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'217; CHECK-NEXT: bytesInStackArgArea: 0218; CHECK-NEXT: returnsVoid: true219; CHECK-NEXT: argumentInfo:220; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }221; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }222; CHECK-NEXT: queuePtr: { reg: '$sgpr6_sgpr7' }223; CHECK-NEXT: dispatchID: { reg: '$sgpr10_sgpr11' }224; CHECK-NEXT: workGroupIDX: { reg: '$sgpr12' }225; CHECK-NEXT: workGroupIDY: { reg: '$sgpr13' }226; CHECK-NEXT: workGroupIDZ: { reg: '$sgpr14' }227; CHECK-NEXT: LDSKernelId: { reg: '$sgpr15' }228; CHECK-NEXT: implicitArgPtr: { reg: '$sgpr8_sgpr9' }229; CHECK-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 }230; CHECK-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 }231; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 }232; CHECK-NEXT: psInputAddr: 0233; CHECK-NEXT: psInputEnable: 0234; CHECK-NEXT: maxMemoryClusterDWords: 8235; CHECK-NEXT: mode:236; CHECK-NEXT: ieee: true237; CHECK-NEXT: dx10-clamp: true238; CHECK-NEXT: fp32-input-denormals: true239; CHECK-NEXT: fp32-output-denormals: true240; CHECK-NEXT: fp64-fp16-input-denormals: true241; CHECK-NEXT: fp64-fp16-output-denormals: true242; CHECK-NEXT: highBitsOf32BitAddress: 0243; CHECK-NEXT: occupancy: 10244; CHECK-NEXT: vgprForAGPRCopy: ''245; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'246; CHECK-NEXT: longBranchReservedReg: ''247; CHECK-NEXT: hasInitWholeWave: false248; CHECK-NEXT: dynamicVGPRBlockSize: 0249; CHECK-NEXT: scratchReservedForDynamicVGPRs: 0250; CHECK-NEXT: numKernargPreloadSGPRs: 0251; CHECK-NEXT: isWholeWaveFunction: false252; CHECK-NEXT: body:253define void @function_nsz() #0 {254 ret void255}256 257; CHECK-LABEL: {{^}}name: function_dx10_clamp_off258; CHECK: mode:259; CHECK-NEXT: ieee: true260; CHECK-NEXT: dx10-clamp: false261; CHECK-NEXT: fp32-input-denormals: true262; CHECK-NEXT: fp32-output-denormals: true263; CHECK-NEXT: fp64-fp16-input-denormals: true264; CHECK-NEXT: fp64-fp16-output-denormals: true265define void @function_dx10_clamp_off() #1 {266 ret void267}268 269; CHECK-LABEL: {{^}}name: function_ieee_off270; CHECK: mode:271; CHECK-NEXT: ieee: false272; CHECK-NEXT: dx10-clamp: true273; CHECK-NEXT: fp32-input-denormals: true274; CHECK-NEXT: fp32-output-denormals: true275; CHECK-NEXT: fp64-fp16-input-denormals: true276; CHECK-NEXT: fp64-fp16-output-denormals: true277define void @function_ieee_off() #2 {278 ret void279}280 281; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off282; CHECK: mode:283; CHECK-NEXT: ieee: false284; CHECK-NEXT: dx10-clamp: false285; CHECK-NEXT: fp32-input-denormals: true286; CHECK-NEXT: fp32-output-denormals: true287; CHECK-NEXT: fp64-fp16-input-denormals: true288; CHECK-NEXT: fp64-fp16-output-denormals: true289define void @function_ieee_off_dx10_clamp_off() #3 {290 ret void291}292 293; CHECK-LABEL: {{^}}name: high_address_bits294; CHECK: machineFunctionInfo:295; CHECK: highBitsOf32BitAddress: 4294934528296define amdgpu_ps void @high_address_bits() #4 {297 ret void298}299 300; CHECK-LABEL: {{^}}name: wwm_reserved_regs301; CHECK: wwmReservedRegs:302; CHECK-NEXT: - '$vgpr2'303; CHECK-NEXT: - '$vgpr3'304define amdgpu_cs void @wwm_reserved_regs(ptr addrspace(1) %ptr, <4 x i32> inreg %tmp14) {305 %ld0 = load volatile i32, ptr addrspace(1) %ptr306 %ld1 = load volatile i32, ptr addrspace(1) %ptr307 %inactive0 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %ld1, i32 0)308 %inactive1 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %ld0, i32 0)309 %wwm0 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %inactive0)310 %wwm1 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %inactive1)311 store volatile i32 %wwm0, ptr addrspace(1) %ptr312 store volatile i32 %wwm1, ptr addrspace(1) %ptr313 ret void314}315 316declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #6317declare i32 @llvm.amdgcn.strict.wwm.i32(i32) #6318 319attributes #0 = { "no-signed-zeros-fp-math" = "true" }320attributes #1 = { "amdgpu-dx10-clamp" = "false" }321attributes #2 = { "amdgpu-ieee" = "false" }322attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" }323attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }324attributes #5 = { "amdgpu-gds-size"="4096" }325attributes #6 = { convergent nounwind readnone willreturn }326attributes #7 = { "InitialPSInputAddr"="36983" }327