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1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -stop-after=amdgpu-isel %s -o - | FileCheck --check-prefix=MIR %s2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -stop-after=amdgpu-isel -o %t.mir %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -start-after=amdgpu-isel -verify-machineinstrs %t.mir -o - | FileCheck --check-prefix=ASM %s4 5; Test that kernarg preloading information is correctly serialized to MIR and6; can be round-tripped through MIR serialization/deserialization.7 8; MIR-LABEL: name: kernarg_preload_single_arg9; MIR: machineFunctionInfo:10; MIR: argumentInfo:11; MIR: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }12; MIR: firstKernArgPreloadReg: { reg: '$sgpr8' }13; MIR: numKernargPreloadSGPRs: 114 15; ASM-LABEL: kernarg_preload_single_arg:16; ASM: .amdhsa_user_sgpr_kernarg_preload_length 117; ASM: .amdhsa_user_sgpr_kernarg_preload_offset 018define amdgpu_kernel void @kernarg_preload_single_arg(i32 inreg %arg0) {19entry:20 %val = add i32 %arg0, 121 store i32 %val, ptr addrspace(1) null22 ret void23}24 25; MIR-LABEL: name: kernarg_preload_multiple_args_unaligned26; MIR: machineFunctionInfo:27; MIR: argumentInfo:28; MIR: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }29; MIR: firstKernArgPreloadReg: { reg: '$sgpr8' }30; MIR: numKernargPreloadSGPRs: 531 32; ASM-LABEL: kernarg_preload_multiple_args_unaligned:33; ASM: .amdhsa_user_sgpr_kernarg_preload_length 534; ASM: .amdhsa_user_sgpr_kernarg_preload_offset 035define amdgpu_kernel void @kernarg_preload_multiple_args_unaligned(i32 inreg %arg0, i64 inreg %arg1, i32 inreg %arg2) {36entry:37 %val = add i32 %arg0, %arg238 store i32 %val, ptr addrspace(1) null39 ret void40}41 42; MIR-LABEL: name: kernarg_preload_multiple_args_aligned43; MIR: machineFunctionInfo:44; MIR: argumentInfo:45; MIR: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }46; MIR: firstKernArgPreloadReg: { reg: '$sgpr8' }47; MIR: numKernargPreloadSGPRs: 448 49; ASM-LABEL: kernarg_preload_multiple_args_aligned:50; ASM: .amdhsa_user_sgpr_kernarg_preload_length 451; ASM: .amdhsa_user_sgpr_kernarg_preload_offset 052define amdgpu_kernel void @kernarg_preload_multiple_args_aligned(i64 inreg %arg0, i32 inreg %arg1, i32 inreg %arg2) {53entry:54 %val = add i32 %arg1, %arg255 store i32 %val, ptr addrspace(1) null56 ret void57}58 59; MIR-LABEL: name: kernarg_preload_with_ptr60; MIR: machineFunctionInfo:61; MIR: argumentInfo:62; MIR: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }63; MIR: firstKernArgPreloadReg: { reg: '$sgpr8' }64; MIR: numKernargPreloadSGPRs: 265 66; ASM-LABEL: kernarg_preload_with_ptr:67; ASM: .amdhsa_user_sgpr_kernarg_preload_length 268; ASM: .amdhsa_user_sgpr_kernarg_preload_offset 069define amdgpu_kernel void @kernarg_preload_with_ptr(ptr inreg %ptr) {70entry:71 %val = load i32, ptr %ptr72 %add = add i32 %val, 173 store i32 %add, ptr %ptr74 ret void75}76 77; MIR-LABEL: name: kernarg_no_preload78; MIR: machineFunctionInfo:79; MIR: argumentInfo:80; MIR: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }81; MIR-NOT: firstKernArgPreloadReg82; MIR: numKernargPreloadSGPRs: 083 84; ASM-LABEL: kernarg_no_preload:85; ASM: .amdhsa_user_sgpr_kernarg_preload_length 086define amdgpu_kernel void @kernarg_no_preload(i32 %arg0) {87entry:88 %val = add i32 %arg0, 189 store i32 %val, ptr addrspace(1) null90 ret void91}92 93; MIR-LABEL: name: kernarg_preload_mixed94; MIR: machineFunctionInfo:95; MIR: argumentInfo:96; MIR: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }97; MIR: firstKernArgPreloadReg: { reg: '$sgpr8' }98; MIR: numKernargPreloadSGPRs: 299 100; ASM-LABEL: kernarg_preload_mixed:101; ASM: .amdhsa_user_sgpr_kernarg_preload_length 2102define amdgpu_kernel void @kernarg_preload_mixed(i32 inreg %arg0, i32 inreg %arg1, i32 %arg2) {103entry:104 %val = add i32 %arg0, %arg1105 %val2 = add i32 %val, %arg2106 store i32 %val2, ptr addrspace(1) null107 ret void108}109 110; MIR-LABEL: name: kernarg_preload_with_dispatch_ptr111; MIR: machineFunctionInfo:112; MIR: argumentInfo:113; MIR: dispatchPtr: { reg: '$sgpr0_sgpr1' }114; MIR: kernargSegmentPtr: { reg: '$sgpr2_sgpr3' }115; MIR: firstKernArgPreloadReg: { reg: '$sgpr4' }116; MIR: numKernargPreloadSGPRs: 2117 118; ASM-LABEL: kernarg_preload_with_dispatch_ptr:119; ASM: .amdhsa_user_sgpr_dispatch_ptr 1120; ASM: .amdhsa_user_sgpr_kernarg_preload_length 2121 122define amdgpu_kernel void @kernarg_preload_with_dispatch_ptr(i64 inreg %arg0) #0 {123entry:124 %val = add i64 %arg0, 1125 store i64 %val, ptr addrspace(1) null126 ret void127}128 129attributes #0 = { "amdgpu-dispatch-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-dispatch-id" }130 131; MIR-LABEL: name: kernarg_preload_with_queue_ptr132; MIR: machineFunctionInfo:133; MIR: argumentInfo:134; MIR: queuePtr: { reg: '$sgpr0_sgpr1' }135; MIR: kernargSegmentPtr: { reg: '$sgpr2_sgpr3' }136; MIR: firstKernArgPreloadReg: { reg: '$sgpr4' }137; MIR: numKernargPreloadSGPRs: 1138 139; ASM-LABEL: kernarg_preload_with_queue_ptr:140; ASM: .amdhsa_user_sgpr_queue_ptr 1141; ASM: .amdhsa_user_sgpr_kernarg_preload_length 1142 143define amdgpu_kernel void @kernarg_preload_with_queue_ptr(i32 inreg %arg0) #1 {144entry:145 %val = add i32 %arg0, 1146 store i32 %val, ptr addrspace(1) null147 ret void148}149 150attributes #1 = { "amdgpu-queue-ptr" "amdgpu-no-dispatch-ptr" "amdgpu-no-dispatch-id" }151 152; MIR-LABEL: name: kernarg_preload_with_multiple_user_sgprs153; MIR: machineFunctionInfo:154; MIR: argumentInfo:155; MIR: dispatchPtr: { reg: '$sgpr0_sgpr1' }156; MIR: queuePtr: { reg: '$sgpr2_sgpr3' }157; MIR: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }158; MIR: dispatchID: { reg: '$sgpr6_sgpr7' }159; MIR: firstKernArgPreloadReg: { reg: '$sgpr8' }160; MIR: numKernargPreloadSGPRs: 2161 162; ASM-LABEL: kernarg_preload_with_multiple_user_sgprs:163; ASM: .amdhsa_user_sgpr_dispatch_ptr 1164; ASM: .amdhsa_user_sgpr_queue_ptr 1165; ASM: .amdhsa_user_sgpr_dispatch_id 1166; ASM: .amdhsa_user_sgpr_kernarg_preload_length 2167 168define amdgpu_kernel void @kernarg_preload_with_multiple_user_sgprs(i64 inreg %arg0) #5 {169entry:170 %val = add i64 %arg0, 1171 store i64 %val, ptr addrspace(1) null172 ret void173}174 175attributes #2 = { "amdgpu-dispatch-ptr" "amdgpu-queue-ptr" "amdgpu-dispatch-id" }176 177; MIR-LABEL: name: kernarg_preload_without_user_sgprs178; MIR: machineFunctionInfo:179; MIR: argumentInfo:180; MIR: kernargSegmentPtr: { reg: '$sgpr0_sgpr1' }181; MIR: firstKernArgPreloadReg: { reg: '$sgpr2' }182; MIR: numKernargPreloadSGPRs: 1183 184; ASM-LABEL: kernarg_preload_without_user_sgprs:185; ASM: .amdhsa_user_sgpr_kernarg_preload_length 1186 187define amdgpu_kernel void @kernarg_preload_without_user_sgprs(i32 inreg %arg0) #3 {188entry:189 %val = add i32 %arg0, 1190 store i32 %val, ptr addrspace(1) null191 ret void192}193 194attributes #3 = { "amdgpu-no-queue-ptr" "amdgpu-no-dispatch-ptr" "amdgpu-no-dispatch-id" }195 196; MIR-LABEL: name: kernarg_preload_max_args197; MIR: machineFunctionInfo:198; MIR: argumentInfo:199; MIR: dispatchPtr: { reg: '$sgpr0_sgpr1' }200; MIR: queuePtr: { reg: '$sgpr2_sgpr3' }201; MIR: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }202; MIR: dispatchID: { reg: '$sgpr6_sgpr7' }203; MIR: firstKernArgPreloadReg: { reg: '$sgpr8' }204; MIR: numKernargPreloadSGPRs: 8205 206; ASM-LABEL: kernarg_preload_max_args:207; ASM: .amdhsa_user_sgpr_kernarg_preload_length 8208 209define amdgpu_kernel void @kernarg_preload_max_args(210 i32 inreg %a0, i32 inreg %a1, i32 inreg %a2, i32 inreg %a3,211 i32 inreg %a4, i32 inreg %a5, i32 inreg %a6, i32 inreg %a7,212 i32 inreg %a8, i32 inreg %a9, i32 inreg %a10, i32 inreg %a11,213 i32 inreg %a12, i32 inreg %a13, i32 inreg %a14, i32 inreg %a15) {214entry:215 ret void216}217 218; MIR-LABEL: name: kernarg_preload_mixed_inreg_and_stack219; MIR: machineFunctionInfo:220; MIR: argumentInfo:221; MIR: firstKernArgPreloadReg: { reg: '$sgpr8' }222; MIR: numKernargPreloadSGPRs: 2223 224; ASM-LABEL: kernarg_preload_mixed_inreg_and_stack:225; ASM: .amdhsa_user_sgpr_kernarg_preload_length 2226 227define amdgpu_kernel void @kernarg_preload_mixed_inreg_and_stack(228 i32 inreg %preload0,229 i32 inreg %preload1,230 i32 %stack0,231 i32 %stack1) {232entry:233 %val = add i32 %preload0, %preload1234 %val2 = add i32 %val, %stack0235 %val3 = add i32 %val2, %stack1236 store i32 %val3, ptr addrspace(1) null237 ret void238}239 240; MIR-LABEL: name: kernarg_preload_vector_types241; MIR: machineFunctionInfo:242; MIR: argumentInfo:243; MIR: firstKernArgPreloadReg: { reg: '$sgpr8' }244; MIR: numKernargPreloadSGPRs: 4245 246; ASM-LABEL: kernarg_preload_vector_types:247; ASM: .amdhsa_user_sgpr_kernarg_preload_length 4248 249define amdgpu_kernel void @kernarg_preload_vector_types(<4 x i32> inreg %vec) {250entry:251 %elem = extractelement <4 x i32> %vec, i32 0252 store i32 %elem, ptr addrspace(1) null253 ret void254}255