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1# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s2# This test verifies that the MIR parser can parse target index operands.3 4--- |5 6 %struct.foo = type { float, [5 x i32] }7 8 @float_gv = internal unnamed_addr addrspace(4) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 49 10 define amdgpu_kernel void @float(ptr addrspace(1) %out, i32 %index) #0 {11 entry:12 %0 = getelementptr inbounds [5 x float], ptr addrspace(4) @float_gv, i32 0, i32 %index13 %1 = load float, ptr addrspace(4) %014 store float %1, ptr addrspace(1) %out15 ret void16 }17 18 define amdgpu_kernel void @float2(ptr addrspace(1) %out, i32 %index) #0 {19 entry:20 %0 = getelementptr inbounds [5 x float], ptr addrspace(4) @float_gv, i32 0, i32 %index21 %1 = load float, ptr addrspace(4) %022 store float %1, ptr addrspace(1) %out23 ret void24 }25 attributes #0 = { nounwind }26 27...28---29name: float30liveins:31 - { reg: '$sgpr0_sgpr1' }32frameInfo:33 maxAlignment: 834body: |35 bb.0.entry:36 liveins: $sgpr0_sgpr137 38 $sgpr2_sgpr3 = S_GETPC_B6439 ; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc40 $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc41 $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc42 $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc43 $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 044 $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc45 $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc46 $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc47 $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc48 $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc49 $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc50 $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 051 $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 052 $sgpr7 = S_MOV_B32 6144053 $sgpr6 = S_MOV_B32 -154 $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec55 BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec56 S_ENDPGM 057...58---59name: float260liveins:61 - { reg: '$sgpr0_sgpr1' }62frameInfo:63 maxAlignment: 864body: |65 bb.0.entry:66 liveins: $sgpr0_sgpr167 68 $sgpr2_sgpr3 = S_GETPC_B6469 ; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc70 $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc71 $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc72 $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc73 $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 074 $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc75 $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc76 $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc77 $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc78 $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc79 $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc80 $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 081 $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 082 $sgpr7 = S_MOV_B32 6144083 $sgpr6 = S_MOV_B32 -184 $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec85 BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec86 S_ENDPGM 087...88