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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P56003 4# Check there are no COPY instructions surrounding ADDVI_W instruction.5# MIParser sets RegClassOrRegBank for parsed virtual registers.6# Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)7# gets selected into ADDVI_W works as expected.8# Check that setRegClassOrRegBank.ll has same output.9 10--- |11 12 declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)13 define void @add_v4i32_builtin_imm(ptr %a, ptr %c) { entry: ret void }14 15...16---17name: add_v4i32_builtin_imm18alignment: 419tracksRegLiveness: true20body: |21 bb.1.entry:22 liveins: $a0, $a123 24 ; P5600-LABEL: name: add_v4i32_builtin_imm25 ; P5600: liveins: $a0, $a126 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a027 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a128 ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)29 ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 2530 ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)31 ; P5600: RetRA32 %0:_(p0) = COPY $a033 %1:_(p0) = COPY $a134 %2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)35 %3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 2536 G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)37 RetRA38 39...40