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1# RUN: llc -mtriple=nvptx -mcpu=sm_20 -run-pass none -o - %s | FileCheck %s2# This test ensures that the MIR parser parses floating point constant operands3# correctly.4 5--- |6 7 define float @test(float %k, i32 %i) {8 entry:9 %0 = fpext float %k to double10 %1 = fadd double %0, 3.250000e+0011 %2 = fptrunc double %1 to float12 %3 = sitofp i32 %i to float13 %4 = fadd float %3, 6.250000e+0014 %5 = fmul float %4, %215 ret float %516 }17 18 define float @test2(float %k, i32 %i) {19 entry:20 %0 = fpext float %k to double21 %1 = fadd double %0, 0x7FF800000000000022 %2 = fptrunc double %1 to float23 %3 = sitofp i32 %i to float24 %4 = fadd float %3, 0x7FF800000000000025 %5 = fmul float %4, %226 ret float %527 }28 29...30---31name: test32registers:33 - { id: 0, class: b32 }34 - { id: 1, class: b64 }35 - { id: 2, class: b32 }36 - { id: 3, class: b64 }37 - { id: 4, class: b32 }38 - { id: 5, class: b32 }39 - { id: 6, class: b32 }40 - { id: 7, class: b32 }41body: |42 bb.0.entry:43 %0 = LD_i32 0, 0, 4, 2, 32, -1, &test_param_0, 044 %1 = CVT_f64_f32 %0, 045 %2 = LD_i32 0, 0, 4, 0, 32, -1, &test_param_1, 046 ; CHECK: %3:b64 = FADD_rnf64ri %1, double 3.250000e+0047 %3 = FADD_rnf64ri %1, double 3.250000e+0048 %4 = CVT_f32_f64 %3, 549 %5 = CVT_f32_s32 %2, 550 ; CHECK: %6:b32 = FADD_rnf32ri %5, float 6.250000e+0051 %6 = FADD_rnf32ri %5, float 6.250000e+00, 052 %7 = FMUL_rnf32rr %6, %4, 053 ST_i32 %7, 0, 0, 101, 32, &func_retval0, 0 :: (store (s32), addrspace 101)54 Return55...56---57name: test258registers:59 - { id: 0, class: b32 }60 - { id: 1, class: b64 }61 - { id: 2, class: b32 }62 - { id: 3, class: b64 }63 - { id: 4, class: b32 }64 - { id: 5, class: b32 }65 - { id: 6, class: b32 }66 - { id: 7, class: b32 }67body: |68 bb.0.entry:69 %0 = LD_i32 0, 0, 4, 2, 32, -1, &test2_param_0, 070 %1 = CVT_f64_f32 %0, 071 %2 = LD_i32 0, 0, 4, 0, 32, -1, &test2_param_1, 072 ; CHECK: %3:b64 = FADD_rnf64ri %1, double 0x7FF800000000000073 %3 = FADD_rnf64ri %1, double 0x7FF800000000000074 %4 = CVT_f32_f64 %3, 575 %5 = CVT_f32_s32 %2, 576 ; CHECK: %6:b32 = FADD_rnf32ri %5, float 0x7FF800000000000077 %6 = FADD_rnf32ri %5, float 0x7FF8000000000000, 078 %7 = FMUL_rnf32rr %6, %4, 079 ST_i32 %7, 0, 0, 101, 32, &func_retval0, 0 :: (store (s32), addrspace 101)80 Return81...82