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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s3# This test ensures that the MIR parser parses and prints subregisters index4# operands correctly.5 6--- |7 8 define zeroext i1 @t(i1 %c) {9 entry:10 ret i1 %c11 }12 13...14---15name: t16tracksRegLiveness: true17registers:18 - { id: 0, class: gr32 }19 - { id: 1, class: gr8 }20body: |21 bb.0.entry:22 liveins: $edi, $eax23 ; CHECK-LABEL: name: t24 ; CHECK: liveins: $edi, $eax25 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit27 ; CHECK-NEXT: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi28 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:gr8 = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_8bit_hi29 ; CHECK-NEXT: $ax = COPY [[REG_SEQUENCE]]30 ; CHECK-NEXT: RET64 $ax31 %0 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit32 %1 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi33 %2:gr8 = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi34 $ax = COPY %235 RET64 $ax36...37 38