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1; RUN: llc -O0 < %s | FileCheck %s2 3target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"4target triple = "msp430---elf"5 6@g_double = global double 123.0, align 87@g_float = global float 123.0, align 88@g_i32 = global i32 123, align 89@g_i64 = global i64 456, align 810@g_i16 = global i16 789, align 811 12define float @d2f() #0 {13entry:14; CHECK: d2f:15 16; CHECK: call #__mspabi_cvtdf17 %0 = load volatile double, ptr @g_double, align 818 %1 = fptrunc double %0 to float19 20 ret float %121}22 23define double @f2d() #0 {24entry:25; CHECK: f2d:26 27; CHECK: call #__mspabi_cvtfd28 %0 = load volatile float, ptr @g_float, align 829 %1 = fpext float %0 to double30 31 ret double %132}33 34define i32 @d2l() #0 {35entry:36; CHECK: d2l:37 38; CHECK: call #__mspabi_fixdli39 %0 = load volatile double, ptr @g_double, align 840 %1 = fptosi double %0 to i3241 42 ret i32 %143}44 45define i64 @d2ll() #0 {46entry:47; CHECK: d2ll:48 49; CHECK: call #__mspabi_fixdlli50 %0 = load volatile double, ptr @g_double, align 851 %1 = fptosi double %0 to i6452 53 ret i64 %154}55 56define i32 @d2ul() #0 {57entry:58; CHECK: d2ul:59 60; CHECK: call #__mspabi_fixdul61 %0 = load volatile double, ptr @g_double, align 862 %1 = fptoui double %0 to i3263 64 ret i32 %165}66 67define i64 @d2ull() #0 {68entry:69; CHECK: d2ull:70 71; CHECK: call #__mspabi_fixdull72 %0 = load volatile double, ptr @g_double, align 873 %1 = fptoui double %0 to i6474 75 ret i64 %176}77 78define i32 @f2l() #0 {79entry:80; CHECK: f2l:81 82; CHECK: call #__mspabi_fixfli83 %0 = load volatile float, ptr @g_float, align 884 %1 = fptosi float %0 to i3285 86 ret i32 %187}88 89define i64 @f2ll() #0 {90entry:91; CHECK: f2ll:92 93; CHECK: call #__mspabi_fixflli94 %0 = load volatile float, ptr @g_float, align 895 %1 = fptosi float %0 to i6496 97 ret i64 %198}99 100define i32 @f2ul() #0 {101entry:102; CHECK: f2ul:103 104; CHECK: call #__mspabi_fixful105 %0 = load volatile float, ptr @g_float, align 8106 %1 = fptoui float %0 to i32107 108 ret i32 %1109}110 111define i64 @f2ull() #0 {112entry:113; CHECK: f2ull:114 115; CHECK: call #__mspabi_fixfull116 %0 = load volatile float, ptr @g_float, align 8117 %1 = fptoui float %0 to i64118 119 ret i64 %1120}121 122define double @l2d() #0 {123entry:124; CHECK: l2d:125 126; CHECK: call #__mspabi_fltlid127 %0 = load volatile i32, ptr @g_i32, align 8128 %1 = sitofp i32 %0 to double129 130 ret double %1131}132 133define double @ll2d() #0 {134entry:135; CHECK: ll2d:136 137; CHECK: call #__mspabi_fltllid138 %0 = load volatile i64, ptr @g_i64, align 8139 %1 = sitofp i64 %0 to double140 141 ret double %1142}143 144define double @ul2d() #0 {145entry:146; CHECK: ul2d:147 148; CHECK: call #__mspabi_fltuld149 %0 = load volatile i32, ptr @g_i32, align 8150 %1 = uitofp i32 %0 to double151 152 ret double %1153}154 155define double @ull2d() #0 {156entry:157; CHECK: ull2d:158 159; CHECK: call #__mspabi_fltulld160 %0 = load volatile i64, ptr @g_i64, align 8161 %1 = uitofp i64 %0 to double162 163 ret double %1164}165 166define float @l2f() #0 {167entry:168; CHECK: l2f:169 170; CHECK: call #__mspabi_fltlif171 %0 = load volatile i32, ptr @g_i32, align 8172 %1 = sitofp i32 %0 to float173 174 ret float %1175}176 177define float @ll2f() #0 {178entry:179; CHECK: ll2f:180 181; CHECK: call #__mspabi_fltllif182 %0 = load volatile i64, ptr @g_i64, align 8183 %1 = sitofp i64 %0 to float184 185 ret float %1186}187 188define float @ul2f() #0 {189entry:190; CHECK: ul2f:191 192; CHECK: call #__mspabi_fltulf193 %0 = load volatile i32, ptr @g_i32, align 8194 %1 = uitofp i32 %0 to float195 196 ret float %1197}198 199define float @ull2f() #0 {200entry:201; CHECK: ull2f:202 203; CHECK: call #__mspabi_fltullf204 %0 = load volatile i64, ptr @g_i64, align 8205 %1 = uitofp i64 %0 to float206 207 ret float %1208}209 210define i1 @cmpd_oeq() #0 {211entry:212; CHECK: cmpd_oeq:213 214; CHECK: call #__mspabi_cmpd215 %0 = load volatile double, ptr @g_double, align 8216 %1 = fcmp oeq double %0, 123.0217 218 ret i1 %1219}220 221define i1 @cmpd_une() #0 {222entry:223; CHECK: cmpd_une:224 225; CHECK: call #__mspabi_cmpd226 %0 = load volatile double, ptr @g_double, align 8227 %1 = fcmp une double %0, 123.0228 229 ret i1 %1230}231 232define i1 @cmpd_oge() #0 {233entry:234; CHECK: cmpd_oge:235 236; CHECK: call #__mspabi_cmpd237 %0 = load volatile double, ptr @g_double, align 8238 %1 = fcmp oge double %0, 123.0239 240 ret i1 %1241}242 243define i1 @cmpd_olt() #0 {244entry:245; CHECK: cmpd_olt:246 247; CHECK: call #__mspabi_cmpd248 %0 = load volatile double, ptr @g_double, align 8249 %1 = fcmp olt double %0, 123.0250 251 ret i1 %1252}253 254define i1 @cmpd_ole() #0 {255entry:256; CHECK: cmpd_ole:257 258; CHECK: call #__mspabi_cmpd259 %0 = load volatile double, ptr @g_double, align 8260 %1 = fcmp ole double %0, 123.0261 262 ret i1 %1263}264 265define i1 @cmpd_ogt() #0 {266entry:267; CHECK: cmpd_ogt:268 269; CHECK: call #__mspabi_cmpd270 %0 = load volatile double, ptr @g_double, align 8271 %1 = fcmp ogt double %0, 123.0272 273 ret i1 %1274}275 276define i1 @cmpf_oeq() #0 {277entry:278; CHECK: cmpf_oeq:279 280; CHECK: call #__mspabi_cmpf281 %0 = load volatile float, ptr @g_float, align 8282 %1 = fcmp oeq float %0, 123.0283 284 ret i1 %1285}286 287define i1 @cmpf_une() #0 {288entry:289; CHECK: cmpf_une:290 291; CHECK: call #__mspabi_cmpf292 %0 = load volatile float, ptr @g_float, align 8293 %1 = fcmp une float %0, 123.0294 295 ret i1 %1296}297 298define i1 @cmpf_oge() #0 {299entry:300; CHECK: cmpf_oge:301 302; CHECK: call #__mspabi_cmpf303 %0 = load volatile float, ptr @g_float, align 8304 %1 = fcmp oge float %0, 123.0305 306 ret i1 %1307}308 309define i1 @cmpf_olt() #0 {310entry:311; CHECK: cmpf_olt:312 313; CHECK: call #__mspabi_cmpf314 %0 = load volatile float, ptr @g_float, align 8315 %1 = fcmp olt float %0, 123.0316 317 ret i1 %1318}319 320define i1 @cmpf_ole() #0 {321entry:322; CHECK: cmpf_ole:323 324; CHECK: call #__mspabi_cmpf325 %0 = load volatile float, ptr @g_float, align 8326 %1 = fcmp ole float %0, 123.0327 328 ret i1 %1329}330 331define i1 @cmpf_ogt() #0 {332entry:333; CHECK: cmpf_ogt:334 335; CHECK: call #__mspabi_cmpf336 %0 = load volatile float, ptr @g_float, align 8337 %1 = fcmp ogt float %0, 123.0338 339 ret i1 %1340}341 342define double @addd() #0 {343entry:344; CHECK: addd:345 346; CHECK: call #__mspabi_addd347 %0 = load volatile double, ptr @g_double, align 8348 %1 = fadd double %0, 123.0349 350 ret double %1351}352 353define float @addf() #0 {354entry:355; CHECK: addf:356 357; CHECK: call #__mspabi_addf358 %0 = load volatile float, ptr @g_float, align 8359 %1 = fadd float %0, 123.0360 361 ret float %1362}363 364define double @divd() #0 {365entry:366; CHECK: divd:367 368; CHECK: call #__mspabi_divd369 %0 = load volatile double, ptr @g_double, align 8370 %1 = fdiv double %0, 123.0371 372 ret double %1373}374 375define float @divf() #0 {376entry:377; CHECK: divf:378 379; CHECK: call #__mspabi_divf380 %0 = load volatile float, ptr @g_float, align 8381 %1 = fdiv float %0, 123.0382 383 ret float %1384}385 386define double @mpyd() #0 {387entry:388; CHECK: mpyd:389 390; CHECK: call #__mspabi_mpyd391 %0 = load volatile double, ptr @g_double, align 8392 %1 = fmul double %0, 123.0393 394 ret double %1395}396 397define float @mpyf() #0 {398entry:399; CHECK: mpyf:400 401; CHECK: call #__mspabi_mpyf402 %0 = load volatile float, ptr @g_float, align 8403 %1 = fmul float %0, 123.0404 405 ret float %1406}407 408define double @subd() #0 {409entry:410; CHECK: subd:411 412; CHECK: call #__mspabi_subd413 %0 = load volatile double, ptr @g_double, align 8414 %1 = fsub double %0, %0415 416 ret double %1417}418 419define float @subf() #0 {420entry:421; CHECK: subf:422 423; CHECK: call #__mspabi_subf424 %0 = load volatile float, ptr @g_float, align 8425 %1 = fsub float %0, %0426 427 ret float %1428}429 430define i16 @divi() #0 {431entry:432; CHECK: divi:433 434; CHECK: call #__mspabi_divi435 %0 = load volatile i16, ptr @g_i16, align 8436 %1 = load volatile i16, ptr @g_i16, align 8437 %2 = sdiv i16 %0, %1438 439 ret i16 %2440}441 442define i32 @divli() #0 {443entry:444; CHECK: divli:445 446; CHECK: call #__mspabi_divli447 %0 = load volatile i32, ptr @g_i32, align 8448 %1 = load volatile i32, ptr @g_i32, align 8449 %2 = sdiv i32 %0, %1450 451 ret i32 %2452}453 454define i64 @divlli() #0 {455entry:456; CHECK: divlli:457 458; CHECK: call #__mspabi_divlli459 %0 = load volatile i64, ptr @g_i64, align 8460 %1 = load volatile i64, ptr @g_i64, align 8461 %2 = sdiv i64 %0, %1462 463 ret i64 %2464}465 466define i16 @divu() #0 {467entry:468; CHECK: divu:469 470; CHECK: call #__mspabi_divu471 %0 = load volatile i16, ptr @g_i16, align 8472 %1 = load volatile i16, ptr @g_i16, align 8473 %2 = udiv i16 %0, %1474 475 ret i16 %2476}477 478define i32 @divul() #0 {479entry:480; CHECK: divul:481 482; CHECK: call #__mspabi_divul483 %0 = load volatile i32, ptr @g_i32, align 8484 %1 = load volatile i32, ptr @g_i32, align 8485 %2 = udiv i32 %0, %1486 487 ret i32 %2488}489 490define i64 @divull() #0 {491entry:492; CHECK: divull:493 494; CHECK: call #__mspabi_divull495 %0 = load volatile i64, ptr @g_i64, align 8496 %1 = load volatile i64, ptr @g_i64, align 8497 %2 = udiv i64 %0, %1498 499 ret i64 %2500}501 502define i16 @remi() #0 {503entry:504; CHECK: remi:505 506; CHECK: call #__mspabi_remi507 %0 = load volatile i16, ptr @g_i16, align 8508 %1 = load volatile i16, ptr @g_i16, align 8509 %2 = srem i16 %0, %1510 511 ret i16 %2512}513 514define i32 @remli() #0 {515entry:516; CHECK: remli:517 518; CHECK: call #__mspabi_remli519 %0 = load volatile i32, ptr @g_i32, align 8520 %1 = load volatile i32, ptr @g_i32, align 8521 %2 = srem i32 %0, %1522 523 ret i32 %2524}525 526define i64 @remlli() #0 {527entry:528; CHECK: remlli:529 530; CHECK: call #__mspabi_remlli531 %0 = load volatile i64, ptr @g_i64, align 8532 %1 = load volatile i64, ptr @g_i64, align 8533 %2 = srem i64 %0, %1534 535 ret i64 %2536}537 538define i16 @remu() #0 {539entry:540; CHECK: remu:541 542; CHECK: call #__mspabi_remu543 %0 = load volatile i16, ptr @g_i16, align 8544 %1 = load volatile i16, ptr @g_i16, align 8545 %2 = urem i16 %0, %1546 547 ret i16 %2548}549 550define i32 @remul() #0 {551entry:552; CHECK: remul:553 554; CHECK: call #__mspabi_remul555 %0 = load volatile i32, ptr @g_i32, align 8556 %1 = load volatile i32, ptr @g_i32, align 8557 %2 = urem i32 %0, %1558 559 ret i32 %2560}561 562define i64 @remull() #0 {563entry:564; CHECK: remull:565 566; CHECK: call #__mspabi_remull567 %0 = load volatile i64, ptr @g_i64, align 8568 %1 = load volatile i64, ptr @g_i64, align 8569 %2 = urem i64 %0, %1570 571 ret i64 %2572}573 574define i16 @mpyi() #0 {575entry:576; CHECK: mpyi:577 578; CHECK: call #__mspabi_mpyi579 %0 = load volatile i16, ptr @g_i16, align 8580 %1 = mul i16 %0, %0581 582 ret i16 %1583}584 585define i32 @mpyli() #0 {586entry:587; CHECK: mpyli:588 589; CHECK: call #__mspabi_mpyl590 %0 = load volatile i32, ptr @g_i32, align 8591 %1 = mul i32 %0, %0592 593 ret i32 %1594}595 596define i64 @mpylli() #0 {597entry:598; CHECK: mpylli:599 600; CHECK: call #__mspabi_mpyll601 %0 = load volatile i64, ptr @g_i64, align 8602 %1 = mul i64 %0, %0603 604 ret i64 %1605}606 607@i = external global i32, align 2608 609define i32 @srll() #0 {610entry:611; CHECK-LABEL: srll:612; CHECK: call #__mspabi_srll613 %0 = load volatile i32, ptr @g_i32, align 2614 %1 = load volatile i32, ptr @i, align 2615 %shr = lshr i32 %0, %1616 617 ret i32 %shr618}619 620define i32 @sral() #0 {621entry:622; CHECK-LABEL: sral:623; CHECK: call #__mspabi_sral624 %0 = load volatile i32, ptr @g_i32, align 2625 %1 = load volatile i32, ptr @i, align 2626 %shr = ashr i32 %0, %1627 628 ret i32 %shr629}630 631define i32 @slll() #0 {632entry:633; CHECK-LABEL: slll:634; CHECK: call #__mspabi_slll635 %0 = load volatile i32, ptr @g_i32, align 2636 %1 = load volatile i32, ptr @i, align 2637 %shr = shl i32 %0, %1638 639 ret i32 %shr640}641 642define i64 @test__mspabi_divull(i64 %a, i64 %b) #0 {643; CHECK-LABEL: test__mspabi_divull:644; CHECK: call #__mspabi_divull645 %result = udiv i64 %a, %b646 ret i64 %result647}648 649define i64 @test__mspabi_remull(i64 %a, i64 %b) #0 {650; CHECK-LABEL: test__mspabi_remull:651; CHECK: call #__mspabi_remull652 %result = urem i64 %a, %b653 ret i64 %result654}655 656attributes #0 = { nounwind }657