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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=msp430-- < %s | FileCheck %s3 4; Check the following conversion in TargetLowering::SimplifySetCC5; (X & 8) != 0 --> (X & 8) >> 36define i16 @testSimplifySetCC_0(i16 %x) {7; CHECK-LABEL: testSimplifySetCC_0:8; CHECK: ; %bb.0: ; %entry9; CHECK-NEXT: bit #32, r1210; CHECK-NEXT: mov r2, r1211; CHECK-NEXT: and #1, r1212; CHECK-NEXT: ret13entry:14 %and = and i16 %x, 3215 %cmp = icmp ne i16 %and, 016 %conv = zext i1 %cmp to i1617 ret i16 %conv18}19 20; Check the following conversion in TargetLowering::SimplifySetCC21; (X & 8) == 8 --> (X & 8) >> 322define i16 @testSimplifySetCC_1(i16 %x) {23; CHECK-LABEL: testSimplifySetCC_1:24; CHECK: ; %bb.0: ; %entry25; CHECK-NEXT: bit #32, r1226; CHECK-NEXT: mov r2, r1227; CHECK-NEXT: and #1, r1228; CHECK-NEXT: ret29entry:30 %and = and i16 %x, 3231 %cmp = icmp eq i16 %and, 3232 %conv = zext i1 %cmp to i1633 ret i16 %conv34}35 36; Check the following conversion in DAGCombiner::SimplifySelectCC37; (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)38define i16 @testSimplifySelectCC_0(i16 %x, i16 %a) {39; CHECK-LABEL: testSimplifySelectCC_0:40; CHECK: ; %bb.0: ; %entry41; CHECK-NEXT: mov r12, r1442; CHECK-NEXT: clr r1243; CHECK-NEXT: bit #2048, r1444; CHECK-NEXT: jeq .LBB2_245; CHECK-NEXT: ; %bb.1: ; %entry46; CHECK-NEXT: mov r13, r1247; CHECK-NEXT: .LBB2_2: ; %entry48; CHECK-NEXT: ret49entry:50 %and = and i16 %x, 204851 %cmp = icmp eq i16 %and, 052 %cond = select i1 %cmp, i16 0, i16 %a53 ret i16 %cond54}55 56; Check the following conversion in DAGCombiner foldExtendedSignBitTest57; sext i1 (setgt iN X, -1) --> sra (not X), (N - 1)58define i16 @testExtendSignBit_0(i16 %x) {59; CHECK-LABEL: testExtendSignBit_0:60; CHECK: ; %bb.0: ; %entry61; CHECK-NEXT: mov r12, r1362; CHECK-NEXT: mov #-1, r1263; CHECK-NEXT: tst r1364; CHECK-NEXT: jge .LBB3_265; CHECK-NEXT: ; %bb.1: ; %entry66; CHECK-NEXT: clr r1267; CHECK-NEXT: .LBB3_2: ; %entry68; CHECK-NEXT: ret69entry:70 %cmp = icmp sgt i16 %x, -171 %cond = sext i1 %cmp to i1672 ret i16 %cond73}74 75; Check the following conversion in DAGCombiner foldExtendedSignBitTest76; zext i1 (setgt iN X, -1) --> srl (not X), (N - 1)77define i16 @testExtendSignBit_1(i16 %x) {78; CHECK-LABEL: testExtendSignBit_1:79; CHECK: ; %bb.0: ; %entry80; CHECK-NEXT: mov r12, r1381; CHECK-NEXT: mov #1, r1282; CHECK-NEXT: tst r1383; CHECK-NEXT: jge .LBB4_284; CHECK-NEXT: ; %bb.1: ; %entry85; CHECK-NEXT: clr r1286; CHECK-NEXT: .LBB4_2: ; %entry87; CHECK-NEXT: ret88entry:89 %cmp = icmp sgt i16 %x, -190 %cond = zext i1 %cmp to i1691 ret i16 %cond92}93 94; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd95; select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A96define i16 @testShiftAnd_0(i16 %x, i16 %a) {97; CHECK-LABEL: testShiftAnd_0:98; CHECK: ; %bb.0: ; %entry99; CHECK-NEXT: tst r12100; CHECK-NEXT: jl .LBB5_2101; CHECK-NEXT: ; %bb.1: ; %entry102; CHECK-NEXT: clr r13103; CHECK-NEXT: .LBB5_2: ; %entry104; CHECK-NEXT: mov r13, r12105; CHECK-NEXT: ret106entry:107 %cmp = icmp slt i16 %x, 0108 %cond = select i1 %cmp, i16 %a, i16 0109 ret i16 %cond110}111 112; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd113; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit114define i16 @testShiftAnd_1(i16 %x) {115; CHECK-LABEL: testShiftAnd_1:116; CHECK: ; %bb.0: ; %entry117; CHECK-NEXT: mov r12, r13118; CHECK-NEXT: mov #2, r12119; CHECK-NEXT: tst r13120; CHECK-NEXT: jl .LBB6_2121; CHECK-NEXT: ; %bb.1: ; %entry122; CHECK-NEXT: clr r12123; CHECK-NEXT: .LBB6_2: ; %entry124; CHECK-NEXT: ret125entry:126 %cmp = icmp slt i16 %x, 0127 %cond = select i1 %cmp, i16 2, i16 0128 ret i16 %cond129}130 131; Check the following conversion in DAGCombiner::SimplifySelectCC132; select C, 16, 0 -> shl C, 4133define i16 @testSimplifySelectCC_1(i16 %a, i16 %b) {134; CHECK-LABEL: testSimplifySelectCC_1:135; CHECK: ; %bb.0: ; %entry136; CHECK-NEXT: mov r12, r14137; CHECK-NEXT: mov #32, r12138; CHECK-NEXT: cmp r14, r13139; CHECK-NEXT: jl .LBB7_2140; CHECK-NEXT: ; %bb.1: ; %entry141; CHECK-NEXT: clr r12142; CHECK-NEXT: .LBB7_2: ; %entry143; CHECK-NEXT: ret144entry:145 %cmp = icmp sgt i16 %a, %b146 %cond = select i1 %cmp, i16 32, i16 0147 ret i16 %cond148}149 150; Check the following conversion in TargetLowering::SimplifySetCC151; (X & 8) != 0 --> (X & 8) >> 3152define i16 @testSimplifySetCC_0_sh8(i16 %x) {153; CHECK-LABEL: testSimplifySetCC_0_sh8:154; CHECK: ; %bb.0: ; %entry155; CHECK-NEXT: and #256, r12156; CHECK-NEXT: swpb r12157; CHECK-NEXT: ret158entry:159 %and = and i16 %x, 256160 %cmp = icmp ne i16 %and, 0161 %conv = zext i1 %cmp to i16162 ret i16 %conv163}164 165; Check the following conversion in TargetLowering::SimplifySetCC166; (X & 8) == 8 --> (X & 8) >> 3167define i16 @testSimplifySetCC_1_sh8(i16 %x) {168; CHECK-LABEL: testSimplifySetCC_1_sh8:169; CHECK: ; %bb.0: ; %entry170; CHECK-NEXT: and #256, r12171; CHECK-NEXT: swpb r12172; CHECK-NEXT: ret173entry:174 %and = and i16 %x, 256175 %cmp = icmp eq i16 %and, 256176 %conv = zext i1 %cmp to i16177 ret i16 %conv178}179 180; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd181; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit182define i16 @testShiftAnd_1_sh8(i16 %x) {183; CHECK-LABEL: testShiftAnd_1_sh8:184; CHECK: ; %bb.0: ; %entry185; CHECK-NEXT: swpb r12186; CHECK-NEXT: and #128, r12187; CHECK-NEXT: ret188entry:189 %cmp = icmp slt i16 %x, 0190 %cond = select i1 %cmp, i16 128, i16 0191 ret i16 %cond192}193 194; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd195; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit196define i16 @testShiftAnd_1_sh9(i16 %x) {197; CHECK-LABEL: testShiftAnd_1_sh9:198; CHECK: ; %bb.0: ; %entry199; CHECK-NEXT: swpb r12200; CHECK-NEXT: mov.b r12, r12201; CHECK-NEXT: clrc202; CHECK-NEXT: rrc r12203; CHECK-NEXT: and #64, r12204; CHECK-NEXT: ret205entry:206 %cmp = icmp slt i16 %x, 0207 %cond = select i1 %cmp, i16 64, i16 0208 ret i16 %cond209}210