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1; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s2; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s3 4%struct.DWstruct = type { i32, i32 }5 6define i32 @A0(i32 %u, i32 %v) nounwind {7entry:8; CHECK: multu 9; CHECK: mflo10; CHECK: mfhi11 %asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},d,d"( i32 %u, i32 %v ) nounwind12 %asmresult = extractvalue %struct.DWstruct %asmtmp, 013 %asmresult1 = extractvalue %struct.DWstruct %asmtmp, 1 ; <i32> [#uses=1]14 %res = add i32 %asmresult, %asmresult115 ret i32 %res16}17 18@gi2 = external global i3219@gi1 = external global i3220@gi0 = external global i3221@gf0 = external global float22@gf1 = external global float23@gd0 = external global double24@gd1 = external global double25 26define void @foo0() nounwind {27entry:28; CHECK: addu29 %0 = load i32, ptr @gi1, align 430 %1 = load i32, ptr @gi0, align 431 %2 = tail call i32 asm "addu $0, $1, $2", "=r,r,r"(i32 %0, i32 %1) nounwind32 store i32 %2, ptr @gi2, align 433 ret void34}35 36define void @foo2() nounwind {37entry:38; CHECK: neg.s39 %0 = load float, ptr @gf1, align 440 %1 = tail call float asm "neg.s $0, $1", "=f,f"(float %0) nounwind41 store float %1, ptr @gf0, align 442 ret void43}44 45define void @foo3() nounwind {46entry:47; CHECK: neg.d48 %0 = load double, ptr @gd1, align 849 %1 = tail call double asm "neg.d $0, $1", "=f,f"(double %0) nounwind50 store double %1, ptr @gd0, align 851 ret void52}53 54; Check that RA doesn't allocate registers in the clobber list.55; CHECK-LABEL: foo4:56; CHECK: #APP57; CHECK-NOT: ulh $258; CHECK: #NO_APP59; CHECK: #APP60; CHECK-NOT: $f061; CHECK: #NO_APP62 63define void @foo4() {64entry:65 %0 = tail call i32 asm sideeffect "ulh $0,16($$sp)\0A\09", "=r,~{$2}"()66 store i32 %0, ptr @gi2, align 467 %1 = load float, ptr @gf0, align 468 %2 = tail call double asm sideeffect "cvt.d.s $0, $1\0A\09", "=f,f,~{$f0}"(float %1)69 store double %2, ptr @gd0, align 870 ret void71}72