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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=mips-- -mattr=-fp64 | FileCheck %s -check-prefix=CHECK-FP323; RUN: llc < %s -mtriple=mips-- -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s -check-prefix=CHECK-FP644 5; This test case is a simplified version of an llvm-stress generated test with6; seed=3718491962.7; It originally failed on MIPS32 with FP64 with the following error:8; LLVM ERROR: ran out of registers during register allocation9; This was caused by impossible register class restrictions caused by the use10; of BuildPairF64 instead of BuildPairF64_64.11 12; FIXME: A redundant mthc1 is currently emitted.13define void @autogen_SD3718491962(double %a0) {14; CHECK-FP32-LABEL: autogen_SD3718491962:15; CHECK-FP32: # %bb.0: # %BB16; CHECK-FP32-NEXT: lui $1, %hi($CPI0_0)17; CHECK-FP32-NEXT: ldc1 $f0, %lo($CPI0_0)($1)18; CHECK-FP32-NEXT: mtc1 $zero, $f219; CHECK-FP32-NEXT: mtc1 $zero, $f320; CHECK-FP32-NEXT: $BB0_1: # %CF8821; CHECK-FP32-NEXT: # =>This Inner Loop Header: Depth=122; CHECK-FP32-NEXT: c.ueq.d $f12, $f023; CHECK-FP32-NEXT: addiu $1, $zero, 124; CHECK-FP32-NEXT: movf $1, $zero, $fcc025; CHECK-FP32-NEXT: c.olt.d $f12, $f226; CHECK-FP32-NEXT: addiu $2, $zero, 127; CHECK-FP32-NEXT: movt $2, $zero, $fcc028; CHECK-FP32-NEXT: and $1, $2, $129; CHECK-FP32-NEXT: bnez $1, $BB0_130; CHECK-FP32-NEXT: nop31; CHECK-FP32-NEXT: # %bb.2: # %CF8532; CHECK-FP32-NEXT: jr $ra33; CHECK-FP32-NEXT: nop34;35; CHECK-FP64-LABEL: autogen_SD3718491962:36; CHECK-FP64: # %bb.0: # %BB37; CHECK-FP64-NEXT: lui $1, %hi($CPI0_0)38; CHECK-FP64-NEXT: ldc1 $f0, %lo($CPI0_0)($1)39; CHECK-FP64-NEXT: mtc1 $zero, $f140; CHECK-FP64-NEXT: mthc1 $zero, $f141; CHECK-FP64-NEXT: $BB0_1: # %CF8842; CHECK-FP64-NEXT: # =>This Inner Loop Header: Depth=143; CHECK-FP64-NEXT: c.ueq.d $f12, $f044; CHECK-FP64-NEXT: addiu $1, $zero, 145; CHECK-FP64-NEXT: movf $1, $zero, $fcc046; CHECK-FP64-NEXT: c.olt.d $f12, $f147; CHECK-FP64-NEXT: addiu $2, $zero, 148; CHECK-FP64-NEXT: movt $2, $zero, $fcc049; CHECK-FP64-NEXT: and $1, $2, $150; CHECK-FP64-NEXT: bnez $1, $BB0_151; CHECK-FP64-NEXT: nop52; CHECK-FP64-NEXT: # %bb.2: # %CF8553; CHECK-FP64-NEXT: jr $ra54; CHECK-FP64-NEXT: nop55BB:56 %Cmp = fcmp ule double 0.000000e+00, %a057 %Cmp11 = fcmp ueq double 0xFDBD965CF1BB7FDA, %a058 br label %CF8859 60CF88: ; preds = %CF8661 %Sl18 = select i1 %Cmp, i1 %Cmp11, i1 %Cmp62 br i1 %Sl18, label %CF88, label %CF8563 64CF85: ; preds = %CF8865 ret void66}67