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1; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \2; RUN: < %s -verify-machineinstrs | FileCheck %s3 4define void @testeq(i32, i32) {5; CHECK-LABEL: testeq:6; CHECK: andi $[[REG0:[0-9]+]], $4, 17; CHECK: andi $[[REG1:[0-9]+]], $5, 18; CHECK: beq $[[REG0]], $[[REG1]],9 %3 = trunc i32 %0 to i110 %4 = trunc i32 %1 to i111 %5 = icmp eq i1 %3, %412 br i1 %5, label %end, label %trap13trap:14 call void @llvm.trap()15 br label %end16end:17 ret void18}19 20 21define void @testne(i32, i32) {22; CHECK-LABEL: testne:23; CHECK: andi $[[REG0:[0-9]+]], $4, 124; CHECK: andi $[[REG1:[0-9]+]], $5, 125; CHECK: bne $[[REG0]], $[[REG1]],26 %3 = trunc i32 %0 to i127 %4 = trunc i32 %1 to i128 %5 = icmp ne i1 %3, %429 br i1 %5, label %end, label %trap30trap:31 call void @llvm.trap()32 br label %end33end:34 ret void35}36 37 38define void @testugt(i32, i32) {39; CHECK-LABEL: testugt:40; CHECK: andi $[[REG0:[0-9]+]], $4, 141; CHECK: andi $[[REG1:[0-9]+]], $5, 142; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]43; CHECK: bnez $[[REG2]],44 %3 = trunc i32 %0 to i145 %4 = trunc i32 %1 to i146 %5 = icmp ugt i1 %3, %447 br i1 %5, label %end, label %trap48trap:49 call void @llvm.trap()50 br label %end51end:52 ret void53}54 55 56define void @testuge(i32, i32) {57; CHECK-LABEL: testuge:58; CHECK: andi $[[REG0:[0-9]+]], $4, 159; CHECK: andi $[[REG1:[0-9]+]], $5, 160; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]61; CHECK: beqz $[[REG2]],62 %3 = trunc i32 %0 to i163 %4 = trunc i32 %1 to i164 %5 = icmp uge i1 %3, %465 br i1 %5, label %end, label %trap66trap:67 call void @llvm.trap()68 br label %end69end:70 ret void71}72 73 74define void @testult(i32, i32) {75; CHECK-LABEL: testult:76; CHECK: andi $[[REG0:[0-9]+]], $4, 177; CHECK: andi $[[REG1:[0-9]+]], $5, 178; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]79; CHECK: bnez $[[REG2]],80 %3 = trunc i32 %0 to i181 %4 = trunc i32 %1 to i182 %5 = icmp ult i1 %3, %483 br i1 %5, label %end, label %trap84trap:85 call void @llvm.trap()86 br label %end87end:88 ret void89}90 91 92define void @testule(i32, i32) {93; CHECK: andi $[[REG0:[0-9]+]], $4, 194; CHECK: andi $[[REG1:[0-9]+]], $5, 195; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]96; CHECK: beqz $[[REG2]],97 %3 = trunc i32 %0 to i198 %4 = trunc i32 %1 to i199 %5 = icmp ule i1 %3, %4100 br i1 %5, label %end, label %trap101trap:102 call void @llvm.trap()103 br label %end104end:105 ret void106}107 108 109define void @testsgt(i32, i32) {110; CHECK-LABEL: testsgt:111; CHECK: andi $[[REG0:[0-9]+]], $4, 1112; CHECK: negu $[[REG2:[0-9]+]], $[[REG0]]113; CHECK: andi $[[REG1:[0-9]+]], $5, 1114; CHECK: negu $[[REG3:[0-9]+]], $[[REG1]]115; CHECK: slt $[[REG4:[0-9]+]], $[[REG3]], $[[REG2]]116; CHECK: bnez $[[REG4]],117 %3 = trunc i32 %0 to i1118 %4 = trunc i32 %1 to i1119 %5 = icmp sgt i1 %3, %4120 br i1 %5, label %end, label %trap121trap:122 call void @llvm.trap()123 br label %end124end:125 ret void126}127 128 129define void @testsge(i32, i32) {130; CHECK-LABEL: testsge:131; CHECK: andi $[[REG0:[0-9]+]], $4, 1132; CHECK: negu $[[REG0]], $[[REG0]]133; CHECK: andi $[[REG1:[0-9]+]], $5, 1134; CHECK: negu $[[REG1]], $[[REG1]]135; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]136; CHECK: beqz $[[REG2]],137 %3 = trunc i32 %0 to i1138 %4 = trunc i32 %1 to i1139 %5 = icmp sge i1 %3, %4140 br i1 %5, label %end, label %trap141trap:142 call void @llvm.trap()143 br label %end144end:145 ret void146}147 148 149define void @testslt(i32, i32) {150; CHECK-LABEL: testslt:151; CHECK: andi $[[REG0:[0-9]+]], $4, 1152; CHECK: negu $[[REG0]], $[[REG0]]153; CHECK: andi $[[REG1:[0-9]+]], $5, 1154; CHECK: negu $[[REG1]], $[[REG1]]155; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]156; CHECK: bnez $[[REG2]],157 %3 = trunc i32 %0 to i1158 %4 = trunc i32 %1 to i1159 %5 = icmp slt i1 %3, %4160 br i1 %5, label %end, label %trap161trap:162 call void @llvm.trap()163 br label %end164end:165 ret void166}167 168 169define void @testsle(i32, i32) {170; CHECK-LABEL: testsle:171; CHECK: andi $[[REG0:[0-9]+]], $4, 1172; CHECK: negu $[[REG2:[0-9]+]], $[[REG0]]173; CHECK: andi $[[REG1:[0-9]+]], $5, 1174; CHECK: negu $[[REG3:[0-9]+]], $[[REG1]]175; CHECK: slt $[[REG4:[0-9]+]], $[[REG3]], $[[REG2]]176; CHECK: beqz $[[REG4]],177 %3 = trunc i32 %0 to i1178 %4 = trunc i32 %1 to i1179 %5 = icmp sle i1 %3, %4180 br i1 %5, label %end, label %trap181trap:182 call void @llvm.trap()183 br label %end184end:185 ret void186}187 188 189declare void @llvm.trap()190