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1; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \2; RUN: -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \4; RUN: -verify-machineinstrs < %s | FileCheck %s5 6@f1 = common global float 0.000000e+00, align 47@f2 = common global float 0.000000e+00, align 48@b1 = common global i32 0, align 49@d1 = common global double 0.000000e+00, align 810@d2 = common global double 0.000000e+00, align 811 12; Function Attrs: nounwind13define void @feq1() {14entry:15 %0 = load float, ptr @f1, align 416 %1 = load float, ptr @f2, align 417 %cmp = fcmp oeq float %0, %118; CHECK-LABEL: feq1:19; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})20; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])21; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})22; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])23; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 024; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 125; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]]26; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc027 28 %conv = zext i1 %cmp to i3229 store i32 %conv, ptr @b1, align 430 ret void31}32 33; Function Attrs: nounwind34define void @fne1() {35entry:36 %0 = load float, ptr @f1, align 437 %1 = load float, ptr @f2, align 438 %cmp = fcmp une float %0, %139; CHECK-LABEL: fne1:40; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})41; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])42; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})43; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])44; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 045; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 146; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]]47; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc048 %conv = zext i1 %cmp to i3249 store i32 %conv, ptr @b1, align 450 ret void51}52 53; Function Attrs: nounwind54define void @flt1() {55entry:56 %0 = load float, ptr @f1, align 457 %1 = load float, ptr @f2, align 458 %cmp = fcmp olt float %0, %159; CHECK-LABEL: flt1:60; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})61; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])62; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})63; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])64; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 065; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 166; CHECK: c.olt.s $f[[REG_F1]], $f[[REG_F2]]67; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc068 69 %conv = zext i1 %cmp to i3270 store i32 %conv, ptr @b1, align 471 ret void72}73 74; Function Attrs: nounwind75define void @fgt1() {76entry:77 %0 = load float, ptr @f1, align 478 %1 = load float, ptr @f2, align 479 %cmp = fcmp ogt float %0, %180; CHECK-LABEL: fgt1:81; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})82; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])83; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})84; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])85; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 086; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 187; CHECK: c.ule.s $f[[REG_F1]], $f[[REG_F2]]88; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc089 %conv = zext i1 %cmp to i3290 store i32 %conv, ptr @b1, align 491 ret void92}93 94; Function Attrs: nounwind95define void @fle1() {96entry:97 %0 = load float, ptr @f1, align 498 %1 = load float, ptr @f2, align 499 %cmp = fcmp ole float %0, %1100; CHECK-LABEL: fle1:101; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})102; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])103; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})104; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])105; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0106; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1107; CHECK: c.ole.s $f[[REG_F1]], $f[[REG_F2]]108; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0109 %conv = zext i1 %cmp to i32110 store i32 %conv, ptr @b1, align 4111 ret void112}113 114; Function Attrs: nounwind115define void @fge1() {116entry:117 %0 = load float, ptr @f1, align 4118 %1 = load float, ptr @f2, align 4119 %cmp = fcmp oge float %0, %1120; CHECK-LABEL: fge1:121; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})122; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])123; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})124; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])125; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0126; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1127; CHECK: c.ult.s $f[[REG_F1]], $f[[REG_F2]]128; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0129 %conv = zext i1 %cmp to i32130 store i32 %conv, ptr @b1, align 4131 ret void132}133 134; Function Attrs: nounwind135define void @deq1() {136entry:137 %0 = load double, ptr @d1, align 8138 %1 = load double, ptr @d2, align 8139 %cmp = fcmp oeq double %0, %1140; CHECK-LABEL: deq1:141; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})142; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])143; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})144; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])145; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0146; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1147; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]]148; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0149 %conv = zext i1 %cmp to i32150 store i32 %conv, ptr @b1, align 4151 ret void152}153 154; Function Attrs: nounwind155define void @dne1() {156entry:157 %0 = load double, ptr @d1, align 8158 %1 = load double, ptr @d2, align 8159 %cmp = fcmp une double %0, %1160; CHECK-LABEL: dne1:161; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})162; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])163; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})164; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])165; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0166; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1167; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]]168; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0169 %conv = zext i1 %cmp to i32170 store i32 %conv, ptr @b1, align 4171 ret void172}173 174; Function Attrs: nounwind175define void @dlt1() {176entry:177 %0 = load double, ptr @d1, align 8178 %1 = load double, ptr @d2, align 8179 %cmp = fcmp olt double %0, %1180; CHECK-LABEL: dlt1:181; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})182; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])183; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})184; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])185; CHECK: addiu $[[REG_ZERO:[0-9]+]], $zero, 0186; CHECK: addiu $[[REG_ONE:[0-9]+]], $zero, 1187; CHECK: c.olt.d $f[[REG_D1]], $f[[REG_D2]]188; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0189 %conv = zext i1 %cmp to i32190 store i32 %conv, ptr @b1, align 4191 ret void192}193 194; Function Attrs: nounwind195define void @dgt1() {196entry:197 %0 = load double, ptr @d1, align 8198 %1 = load double, ptr @d2, align 8199 %cmp = fcmp ogt double %0, %1200; CHECK-LABEL: dgt1:201; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})202; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])203; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})204; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])205; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0206; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1207; CHECK: c.ule.d $f[[REG_D1]], $f[[REG_D2]]208; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0209 %conv = zext i1 %cmp to i32210 store i32 %conv, ptr @b1, align 4211 ret void212}213 214; Function Attrs: nounwind215define void @dle1() {216entry:217 %0 = load double, ptr @d1, align 8218 %1 = load double, ptr @d2, align 8219 %cmp = fcmp ole double %0, %1220; CHECK-LABEL: dle1:221; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})222; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])223; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})224; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])225; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0226; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1227; CHECK: c.ole.d $f[[REG_D1]], $f[[REG_D2]]228; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0229 %conv = zext i1 %cmp to i32230 store i32 %conv, ptr @b1, align 4231 ret void232}233 234; Function Attrs: nounwind235define void @dge1() {236entry:237 %0 = load double, ptr @d1, align 8238 %1 = load double, ptr @d2, align 8239 %cmp = fcmp oge double %0, %1240; CHECK-LABEL: dge1:241; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})242; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])243; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})244; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])245; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0246; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1247; CHECK: c.ult.d $f[[REG_D1]], $f[[REG_D2]]248; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0249 %conv = zext i1 %cmp to i32250 store i32 %conv, ptr @b1, align 4251 ret void252}253 254 255