211 lines · plain
1; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \2; RUN: < %s | FileCheck %s3; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \4; RUN: < %s | FileCheck %s5 6@c = global i32 4, align 47@d = global i32 9, align 48@uc = global i32 4, align 49@ud = global i32 9, align 410@b1 = common global i32 0, align 411 12; Function Attrs: nounwind13define void @eq() {14entry:15; CHECK-LABEL: .ent eq16 17 %0 = load i32, ptr @c, align 418 %1 = load i32, ptr @d, align 419 %cmp = icmp eq i32 %0, %120 %conv = zext i1 %cmp to i3221; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})22; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})23; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])24; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])25; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]26; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 127; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1.28; CHECK: andi ${{[0-9]+}}, $[[REG2]], 129 30 store i32 %conv, ptr @b1, align 431 ret void32}33 34; Function Attrs: nounwind35define void @ne() {36entry:37; CHECK-LABEL: .ent ne38 %0 = load i32, ptr @c, align 439 %1 = load i32, ptr @d, align 440 %cmp = icmp ne i32 %0, %141 %conv = zext i1 %cmp to i3242; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})43; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})44; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])45; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])46; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]47; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]48; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.49; CHECK: andi ${{[0-9]+}}, $[[REG2]], 150 51 store i32 %conv, ptr @b1, align 452 ret void53}54 55; Function Attrs: nounwind56define void @ugt() {57entry:58; CHECK-LABEL: .ent ugt59 %0 = load i32, ptr @uc, align 460 %1 = load i32, ptr @ud, align 461 %cmp = icmp ugt i32 %0, %162 %conv = zext i1 %cmp to i3263; CHECK: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})64; CHECK: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])65; CHECK: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})66; CHECK: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])67; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]68; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.69; CHECK: andi ${{[0-9]+}}, $[[REG1]], 170 71 store i32 %conv, ptr @b1, align 472 ret void73}74 75; Function Attrs: nounwind76define void @ult() {77entry:78; CHECK-LABEL: .ent ult79 %0 = load i32, ptr @uc, align 480 %1 = load i32, ptr @ud, align 481 %cmp = icmp ult i32 %0, %182 %conv = zext i1 %cmp to i3283; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})84; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})85; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])86; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])87; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]88; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.89; CHECK: andi ${{[0-9]+}}, $[[REG1]], 190 store i32 %conv, ptr @b1, align 491 ret void92}93 94; Function Attrs: nounwind95define void @uge() {96entry:97; CHECK-LABEL: .ent uge98 %0 = load i32, ptr @uc, align 499 %1 = load i32, ptr @ud, align 4100 %cmp = icmp uge i32 %0, %1101 %conv = zext i1 %cmp to i32102; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})103; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})104; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])105; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])106; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]107; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1108; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.109; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1110 store i32 %conv, ptr @b1, align 4111 ret void112}113 114; Function Attrs: nounwind115define void @ule() {116entry:117; CHECK-LABEL: .ent ule118 %0 = load i32, ptr @uc, align 4119 %1 = load i32, ptr @ud, align 4120 %cmp = icmp ule i32 %0, %1121 %conv = zext i1 %cmp to i32122; CHECK: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})123; CHECK: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])124; CHECK: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})125; CHECK: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])126; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]127; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1128; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.129; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1130 store i32 %conv, ptr @b1, align 4131 ret void132}133 134; Function Attrs: nounwind135define void @sgt() {136entry:137; CHECK-LABEL: .ent sgt138 %0 = load i32, ptr @c, align 4139 %1 = load i32, ptr @d, align 4140 %cmp = icmp sgt i32 %0, %1141 %conv = zext i1 %cmp to i32142; CHECK: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})143; CHECK: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])144; CHECK: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})145; CHECK: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])146; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]147; FIXME: This instruction is redundant. The slt can only produce 0 and 1.148; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1149 store i32 %conv, ptr @b1, align 4150 ret void151}152 153; Function Attrs: nounwind154define void @slt() {155entry:156; CHECK-LABEL: .ent slt157 %0 = load i32, ptr @c, align 4158 %1 = load i32, ptr @d, align 4159 %cmp = icmp slt i32 %0, %1160 %conv = zext i1 %cmp to i32161; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})162; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})163; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])164; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])165; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]166; FIXME: This instruction is redundant. The slt can only produce 0 and 1.167; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1168 store i32 %conv, ptr @b1, align 4169 ret void170}171 172; Function Attrs: nounwind173define void @sge() {174entry:175; CHECK-LABEL: .ent sge176 %0 = load i32, ptr @c, align 4177 %1 = load i32, ptr @d, align 4178 %cmp = icmp sge i32 %0, %1179 %conv = zext i1 %cmp to i32180 store i32 %conv, ptr @b1, align 4181; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})182; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})183; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])184; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])185; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]186; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1187; FIXME: This instruction is redundant. The slt can only produce 0 and 1.188; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1189 ret void190}191 192; Function Attrs: nounwind193define void @sle() {194entry:195; CHECK-LABEL: .ent sle196 %0 = load i32, ptr @c, align 4197 %1 = load i32, ptr @d, align 4198 %cmp = icmp sle i32 %0, %1199 %conv = zext i1 %cmp to i32200; CHECK: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})201; CHECK: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])202; CHECK: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})203; CHECK: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])204; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]205; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1206; FIXME: This instruction is redundant. The slt can only produce 0 and 1.207; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1208 store i32 %conv, ptr @b1, align 4209 ret void210}211