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1; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \2; RUN: < %s | FileCheck %s3; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \4; RUN: < %s | FileCheck %s5; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \6; RUN: < %s | FileCheck %s -check-prefix=mips32r27; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \8; RUN: < %s | FileCheck %s -check-prefix=mips329 10@b2 = global i8 0, align 111@b1 = global i8 1, align 112@uc1 = global i8 0, align 113@uc2 = global i8 -1, align 114@sc1 = global i8 -128, align 115@sc2 = global i8 127, align 116@ss1 = global i16 -32768, align 217@ss2 = global i16 32767, align 218@us1 = global i16 0, align 219@us2 = global i16 -1, align 220@ssi = global i16 0, align 221@ssj = global i16 0, align 222@i = global i32 0, align 423@j = global i32 0, align 424@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 125@.str1 = private unnamed_addr constant [7 x i8] c"%i %i\0A\00", align 126 27; Function Attrs: nounwind28define void @_Z3b_iv() {29entry:30; CHECK-LABEL: .ent _Z3b_iv31 %0 = load i8, ptr @b1, align 132 %tobool = trunc i8 %0 to i133 %frombool = zext i1 %tobool to i834 store i8 %frombool, ptr @b2, align 135 %1 = load i8, ptr @b2, align 136 %tobool1 = trunc i8 %1 to i137 %conv = zext i1 %tobool1 to i3238 store i32 %conv, ptr @i, align 439; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})40; CHECK: andi $[[REG2:[0-9]+]], $[[REG1]], 141; CHECK: sb $[[REG2]], 0(${{[0-9]+}})42 43 44 45 ret void46; CHECK: .end _Z3b_iv47}48 49; Function Attrs: nounwind50define void @_Z4uc_iv() {51entry:52; CHECK-LABEL: .ent _Z4uc_iv53 54 %0 = load i8, ptr @uc1, align 155 %conv = zext i8 %0 to i3256 store i32 %conv, ptr @i, align 457 %1 = load i8, ptr @uc2, align 158 %conv1 = zext i8 %1 to i3259; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})60; CHECK: andi ${{[0-9]+}}, $[[REG1]], 25561 62 store i32 %conv1, ptr @j, align 463 ret void64; CHECK: .end _Z4uc_iv65 66}67 68; Function Attrs: nounwind69define void @_Z4sc_iv() {70entry:71; mips32r2-LABEL: .ent _Z4sc_iv72; mips32-LABEL: .ent _Z4sc_iv73 74 %0 = load i8, ptr @sc1, align 175 %conv = sext i8 %0 to i3276 store i32 %conv, ptr @i, align 477 %1 = load i8, ptr @sc2, align 178 %conv1 = sext i8 %1 to i3279 store i32 %conv1, ptr @j, align 480; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})81; mips32r2: seb ${{[0-9]+}}, $[[REG1]]82; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})83; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 2484; mips32: sra ${{[0-9]+}}, $[[REG2]], 2485 86 ret void87; CHECK: .end _Z4sc_iv88}89 90; Function Attrs: nounwind91define void @_Z4us_iv() {92entry:93; CHECK-LABEL: .ent _Z4us_iv94 %0 = load i16, ptr @us1, align 295 %conv = zext i16 %0 to i3296 store i32 %conv, ptr @i, align 497 %1 = load i16, ptr @us2, align 298 %conv1 = zext i16 %1 to i3299 store i32 %conv1, ptr @j, align 4100 ret void101; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})102; CHECK: andi ${{[0-9]+}}, $[[REG1]], 65535103; CHECK: .end _Z4us_iv104}105 106; Function Attrs: nounwind107define void @_Z4ss_iv() {108entry:109; mips32r2-LABEL: .ent _Z4ss_iv110; mips32=LABEL: .ent _Z4ss_iv111 112 %0 = load i16, ptr @ss1, align 2113 %conv = sext i16 %0 to i32114 store i32 %conv, ptr @i, align 4115 %1 = load i16, ptr @ss2, align 2116 %conv1 = sext i16 %1 to i32117 store i32 %conv1, ptr @j, align 4118; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})119; mips32r2: seh ${{[0-9]+}}, $[[REG1]]120; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})121; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16122; mips32: sra ${{[0-9]+}}, $[[REG2]], 16123 124 ret void125; CHECK: .end _Z4ss_iv126}127 128; Function Attrs: nounwind129define void @_Z4b_ssv() {130entry:131; CHECK-LABEL: .ent _Z4b_ssv132 %0 = load i8, ptr @b2, align 1133 %tobool = trunc i8 %0 to i1134 %conv = zext i1 %tobool to i16135 store i16 %conv, ptr @ssi, align 2136 ret void137; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})138; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1139; CHECK: .end _Z4b_ssv140}141 142; Function Attrs: nounwind143define void @_Z5uc_ssv() {144entry:145; CHECK-LABEL: .ent _Z5uc_ssv146 %0 = load i8, ptr @uc1, align 1147 %conv = zext i8 %0 to i16148 store i16 %conv, ptr @ssi, align 2149 %1 = load i8, ptr @uc2, align 1150 %conv1 = zext i8 %1 to i16151; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})152; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255153 154 store i16 %conv1, ptr @ssj, align 2155 ret void156; CHECK: .end _Z5uc_ssv157}158 159; Function Attrs: nounwind160define void @_Z5sc_ssv() {161entry:162; mips32r2-LABEL: .ent _Z5sc_ssv163; mips32-LABEL: .ent _Z5sc_ssv164 %0 = load i8, ptr @sc1, align 1165 %conv = sext i8 %0 to i16166 store i16 %conv, ptr @ssi, align 2167 %1 = load i8, ptr @sc2, align 1168 %conv1 = sext i8 %1 to i16169 store i16 %conv1, ptr @ssj, align 2170; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})171; mips32r2: seb ${{[0-9]+}}, $[[REG1]]172; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})173; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24174; mips32: sra ${{[0-9]+}}, $[[REG2]], 24175 176 ret void177; CHECK: .end _Z5sc_ssv178}179 180