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1; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s2; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s3 4@ub1 = common global i8 0, align 15@ub2 = common global i8 0, align 16@ub3 = common global i8 0, align 17@uc1 = common global i8 0, align 18@uc2 = common global i8 0, align 19@uc3 = common global i8 0, align 110@us1 = common global i16 0, align 211@us2 = common global i16 0, align 212@us3 = common global i16 0, align 213@ub = common global i8 0, align 114@uc = common global i8 0, align 115@us = common global i16 0, align 216@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 117@ui = common global i32 0, align 418@ui1 = common global i32 0, align 419@ui2 = common global i32 0, align 420@ui3 = common global i32 0, align 421 22; Function Attrs: noinline nounwind23define void @andUb() #0 {24entry:25 %0 = load i8, ptr @ub1, align 126 %1 = load i8, ptr @ub2, align 127 %conv0 = trunc i8 %0 to i128 %conv1 = trunc i8 %1 to i129 %and0 = and i1 %conv1, %conv030 %conv3 = zext i1 %and0 to i831 store i8 %conv3, ptr @ub, align 1, !tbaa !232; CHECK-LABEL: .ent andUb33; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)34; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)35; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $2536; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])37; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])38; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])39; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])40; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]41; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 142; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])43; CHECK: sb $[[RES]], 0($[[UB_ADDR]])44 ret void45}46 47; Function Attrs: noinline nounwind48define void @andUb0() #0 {49entry:50 %0 = load i8, ptr @ub1, align 1, !tbaa !251 %conv = trunc i8 %0 to i152 %and = and i1 %conv, 053 %conv1 = zext i1 %and to i854 store i8 %conv1, ptr @ub, align 1, !tbaa !255; CHECK-LABEL: .ent andUb056; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)57; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)58; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $2559; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])60; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])61; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $zero62; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 163; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])64; CHECK: sb $[[RES]], 0($[[UB_ADDR]])65; CHECK: .end andUb066 ret void67}68 69; Function Attrs: noinline nounwind70define void @andUb1() #0 {71; clang uses i8 constants for booleans, so we test with an i8 1.72entry:73 %x = load i8, ptr @ub1, align 1, !tbaa !274 %and = and i8 %x, 175 %conv = trunc i8 %and to i176 %conv1 = zext i1 %conv to i877 store i8 %conv1, ptr @ub, align 1, !tbaa !278; CHECK-LABEL: .ent andUb179; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)80; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)81; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $2582; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 183; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])84; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])85; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]86; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 187; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])88; CHECK: sb $[[RES]], 0($[[UB_ADDR]])89; CHECK: .end andUb190 ret void91}92 93; Function Attrs: noinline nounwind94define void @orUb() #0 {95entry:96 %0 = load i8, ptr @ub1, align 197 %1 = load i8, ptr @ub2, align 198 %conv0 = trunc i8 %0 to i199 %conv1 = trunc i8 %1 to i1100 %or0 = or i1 %conv1, %conv0101 %conv3 = zext i1 %or0 to i8102 store i8 %conv3, ptr @ub, align 1, !tbaa !2103; CHECK-LABEL: .ent orUb104; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)105; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)106; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25107; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])108; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])109; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])110; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])111; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]112; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1113; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])114; CHECK: sb $[[RES]], 0($[[UB_ADDR]])115 ret void116}117 118; Function Attrs: noinline nounwind119define void @orUb0() #0 {120entry:121 %0 = load i8, ptr @ub1, align 1, !tbaa !2122 %conv = trunc i8 %0 to i1123 %or = or i1 %conv, 0124 %conv1 = zext i1 %or to i8125 store i8 %conv1, ptr @ub, align 1, !tbaa !2126; CHECK-LABEL: .ent orUb0127; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)128; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)129; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25130; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])131; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])132; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1133; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])134; CHECK: sb $[[RES]], 0($[[UB_ADDR]])135; CHECK: .end orUb0136 ret void137}138 139; Function Attrs: noinline nounwind140define void @orUb1() #0 {141entry:142 %x = load i8, ptr @ub1, align 1, !tbaa !2143 %or = or i8 %x, 1144 %conv = trunc i8 %or to i1145 %conv1 = zext i1 %conv to i8146 store i8 %conv1, ptr @ub, align 1, !tbaa !2147; CHECK-LABEL: .ent orUb1148; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)149; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)150; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25151; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1152; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])153; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])154; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]155; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1156; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])157; CHECK: sb $[[RES]], 0($[[UB_ADDR]])158; CHECK: .end orUb1159 ret void160}161 162; Function Attrs: noinline nounwind163define void @xorUb() #0 {164entry:165 %0 = load i8, ptr @ub1, align 1166 %1 = load i8, ptr @ub2, align 1167 %conv0 = trunc i8 %0 to i1168 %conv1 = trunc i8 %1 to i1169 %xor0 = xor i1 %conv1, %conv0170 %conv3 = zext i1 %xor0 to i8171 store i8 %conv3, ptr @ub, align 1, !tbaa !2172; CHECK-LABEL: .ent xorUb173; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)174; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)175; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25176; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])177; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])178; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])179; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])180; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]181; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1182; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])183; CHECK: sb $[[RES]], 0($[[UB_ADDR]])184 ret void185}186 187; Function Attrs: noinline nounwind188define void @xorUb0() #0 {189entry:190 %0 = load i8, ptr @ub1, align 1, !tbaa !2191 %conv = trunc i8 %0 to i1192 %xor = xor i1 %conv, 0193 %conv1 = zext i1 %xor to i8194 store i8 %conv1, ptr @ub, align 1, !tbaa !2195; CHECK-LABEL: .ent xorUb0196; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)197; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)198; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25199; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])200; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])201; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $zero202; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1203; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])204; CHECK: sb $[[RES]], 0($[[UB_ADDR]])205; CHECK: .end xorUb0206 ret void207}208 209; Function Attrs: noinline nounwind210define void @xorUb1() #0 {211entry:212 %x = load i8, ptr @ub1, align 1, !tbaa !2213 %xor = xor i8 1, %x214 %conv = trunc i8 %xor to i1215 %conv1 = zext i1 %conv to i8216 store i8 %conv1, ptr @ub, align 1, !tbaa !2217; CHECK-LABEL: .ent xorUb1218; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)219; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)220; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25221; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1222; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])223; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])224; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]225; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1226; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])227; CHECK: sb $[[RES]], 0($[[UB_ADDR]])228; CHECK: .end xorUb1229 ret void230}231 232; Function Attrs: noinline nounwind233define void @andUc() #0 {234entry:235 %0 = load i8, ptr @uc1, align 1, !tbaa !2236 %1 = load i8, ptr @uc2, align 1, !tbaa !2237 %and3 = and i8 %1, %0238 store i8 %and3, ptr @uc, align 1, !tbaa !2239; CHECK-LABEL: .ent andUc240; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)241; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)242; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25243; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])244; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])245; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])246; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])247; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])248; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC2]], $[[UC1]]249; CHECK: sb $[[RES]], 0($[[UC_ADDR]])250 ret void251}252 253; Function Attrs: noinline nounwind254define void @andUc0() #0 {255entry:256 %0 = load i8, ptr @uc1, align 1, !tbaa !2257 %and = and i8 %0, 67258 store i8 %and, ptr @uc, align 1, !tbaa !2259; CHECK-LABEL: .ent andUc0260; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)261; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)262; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25263; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])264; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])265; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])266; CHECK-DAG: addiu $[[CONST_67:[0-9]+]], $zero, 67267; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_67]]268; CHECK: sb $[[RES]], 0($[[UC_ADDR]])269; CHECK: .end andUc0270 ret void271}272 273; Function Attrs: noinline nounwind274define void @andUc1() #0 {275entry:276 %0 = load i8, ptr @uc1, align 1, !tbaa !2277 %and = and i8 %0, 167278 store i8 %and, ptr @uc, align 1, !tbaa !2279; CHECK-LABEL: .ent andUc1280; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)281; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)282; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25283; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])284; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])285; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])286; CHECK-DAG: addiu $[[CONST_167:[0-9]+]], $zero, 167287; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_167]]288; CHECK: sb $[[RES]], 0($[[UC_ADDR]])289; CHECK: .end andUc1290 ret void291}292 293; Function Attrs: noinline nounwind294define void @orUc() #0 {295entry:296 %0 = load i8, ptr @uc1, align 1, !tbaa !2297 %1 = load i8, ptr @uc2, align 1, !tbaa !2298 %or3 = or i8 %1, %0299 store i8 %or3, ptr @uc, align 1, !tbaa !2300; CHECK-LABEL: .ent orUc301; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)302; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)303; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25304; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])305; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])306; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])307; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])308; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])309; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC2]], $[[UC1]]310; CHECK: sb $[[RES]], 0($[[UC_ADDR]])311; CHECK: .end orUc312 ret void313}314 315; Function Attrs: noinline nounwind316define void @orUc0() #0 {317entry:318 %0 = load i8, ptr @uc1, align 1, !tbaa !2319 %or = or i8 %0, 69320 store i8 %or, ptr @uc, align 1, !tbaa !2321; CHECK-LABEL: .ent orUc0322; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)323; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)324; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25325; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])326; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])327; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])328; CHECK-DAG: addiu $[[CONST_69:[0-9]+]], $zero, 69329; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_69]]330; CHECK: sb $[[RES]], 0($[[UC_ADDR]])331; CHECK: .end orUc0332 ret void333}334 335; Function Attrs: noinline nounwind336define void @orUc1() #0 {337entry:338 %0 = load i8, ptr @uc1, align 1, !tbaa !2339 %or = or i8 %0, 238340 store i8 %or, ptr @uc, align 1, !tbaa !2341; CHECK-LABEL: .ent orUc1342; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)343; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)344; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25345; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])346; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])347; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])348; CHECK-DAG: addiu $[[CONST_238:[0-9]+]], $zero, 238349; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_238]]350; CHECK: sb $[[RES]], 0($[[UC_ADDR]])351; CHECK: .end orUc1352 ret void353}354 355; Function Attrs: noinline nounwind356define void @xorUc() #0 {357entry:358 %0 = load i8, ptr @uc1, align 1, !tbaa !2359 %1 = load i8, ptr @uc2, align 1, !tbaa !2360 %xor3 = xor i8 %1, %0361 store i8 %xor3, ptr @uc, align 1, !tbaa !2362; CHECK-LABEL: .ent xorUc363; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)364; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)365; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25366; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])367; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])368; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])369; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])370; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])371; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC2]], $[[UC1]]372; CHECK: sb $[[RES]], 0($[[UC_ADDR]])373; CHECK: .end xorUc374 ret void375}376 377; Function Attrs: noinline nounwind378define void @xorUc0() #0 {379entry:380 %0 = load i8, ptr @uc1, align 1, !tbaa !2381 %xor = xor i8 %0, 23382 store i8 %xor, ptr @uc, align 1, !tbaa !2383; CHECK-LABEL: .ent xorUc0384; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)385; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)386; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25387; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])388; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])389; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])390; CHECK-DAG: addiu $[[CONST_23:[0-9]+]], $zero, 23391; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC1]], $[[CONST_23]]392; CHECK: sb $[[RES]], 0($[[UC_ADDR]])393; CHECK: .end xorUc0394 ret void395}396 397; Function Attrs: noinline nounwind398define void @xorUc1() #0 {399entry:400 %0 = load i8, ptr @uc1, align 1, !tbaa !2401 %xor = xor i8 %0, 120402 store i8 %xor, ptr @uc, align 1, !tbaa !2403; CHECK-LABEL: .ent xorUc1404; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)405; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)406; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25407; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])408; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])409; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])410; CHECK-DAG: addiu $[[CONST_120:[0-9]+]], $zero, 120411; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC1]], $[[CONST_120]]412; CHECK: sb $[[RES]], 0($[[UC_ADDR]])413; CHECK: .end xorUc1414 ret void415}416 417; Function Attrs: noinline nounwind418define void @andUs() #0 {419entry:420 %0 = load i16, ptr @us1, align 2, !tbaa !5421 %1 = load i16, ptr @us2, align 2, !tbaa !5422 %and3 = and i16 %1, %0423 store i16 %and3, ptr @us, align 2, !tbaa !5424; CHECK-LABEL: .ent andUs425; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)426; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)427; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25428; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])429; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])430; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])431; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])432; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])433; CHECK-DAG: and $[[RES:[0-9]+]], $[[US2]], $[[US1]]434; CHECK: sh $[[RES]], 0($[[US_ADDR]])435; CHECK: .end andUs436 ret void437}438 439; Function Attrs: noinline nounwind440define void @andUs0() #0 {441entry:442 %0 = load i16, ptr @us1, align 2, !tbaa !5443 %and = and i16 %0, 4660444 store i16 %and, ptr @us, align 2, !tbaa !5445; CHECK-LABEL: .ent andUs0446; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)447; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)448; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25449; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])450; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])451; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])452; CHECK-DAG: addiu $[[CONST_4660:[0-9]+]], $zero, 4660453; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_4660]]454; CHECK: sh $[[RES]], 0($[[US_ADDR]])455; CHECK: .end andUs0456 ret void457}458 459; Function Attrs: noinline nounwind460define void @andUs1() #0 {461entry:462 %0 = load i16, ptr @us1, align 2, !tbaa !5463 %and = and i16 %0, 61351464 store i16 %and, ptr @us, align 2, !tbaa !5465; CHECK-LABEL: .ent andUs1466; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)467; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)468; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25469; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])470; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])471; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])472; CHECK-DAG: ori $[[CONST_61351:[0-9]+]], $zero, 61351473; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_61351]]474; CHECK: sh $[[RES]], 0($[[US_ADDR]])475; CHECK: .end andUs1476 ret void477}478 479; Function Attrs: noinline nounwind480define void @orUs() #0 {481entry:482 %0 = load i16, ptr @us1, align 2, !tbaa !5483 %1 = load i16, ptr @us2, align 2, !tbaa !5484 %or3 = or i16 %1, %0485 store i16 %or3, ptr @us, align 2, !tbaa !5486; CHECK-LABEL: .ent orUs487; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)488; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)489; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25490; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])491; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])492; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])493; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])494; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])495; CHECK-DAG: or $[[RES:[0-9]+]], $[[US2]], $[[US1]]496; CHECK: sh $[[RES]], 0($[[US_ADDR]])497; CHECK: .end orUs498 ret void499}500 501; Function Attrs: noinline nounwind502define void @orUs0() #0 {503entry:504 %0 = load i16, ptr @us1, align 2, !tbaa !5505 %or = or i16 %0, 17666506 store i16 %or, ptr @us, align 2, !tbaa !5507 ret void508}509 510; Function Attrs: noinline nounwind511define void @orUs1() #0 {512entry:513 %0 = load i16, ptr @us1, align 2, !tbaa !5514 %or = or i16 %0, 60945515 store i16 %or, ptr @us, align 2, !tbaa !5516; CHECK-LABEL: .ent orUs1517; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)518; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)519; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25520; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])521; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])522; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])523; CHECK-DAG: ori $[[CONST_60945:[0-9]+]], $zero, 60945524; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_60945]]525; CHECK: sh $[[RES]], 0($[[US_ADDR]])526; CHECK: .end orUs1527 ret void528}529 530; Function Attrs: noinline nounwind531define void @xorUs() #0 {532entry:533 %0 = load i16, ptr @us1, align 2, !tbaa !5534 %1 = load i16, ptr @us2, align 2, !tbaa !5535 %xor3 = xor i16 %1, %0536 store i16 %xor3, ptr @us, align 2, !tbaa !5537; CHECK-LABEL: .ent xorUs538; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)539; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)540; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25541; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])542; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])543; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])544; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])545; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])546; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US2]], $[[US1]]547; CHECK: sh $[[RES]], 0($[[US_ADDR]])548; CHECK: .end xorUs549 ret void550}551 552; Function Attrs: noinline nounwind553define void @xorUs0() #0 {554entry:555 %0 = load i16, ptr @us1, align 2, !tbaa !5556 %xor = xor i16 %0, 6062557 store i16 %xor, ptr @us, align 2, !tbaa !5558; CHECK-LABEL: .ent xorUs0559; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)560; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)561; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25562; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])563; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])564; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])565; CHECK-DAG: addiu $[[CONST_6062:[0-9]+]], $zero, 6062566; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_6062]]567; CHECK: sh $[[RES]], 0($[[US_ADDR]])568; CHECK: .end xorUs0569 570 ret void571}572 573; Function Attrs: noinline nounwind574define void @xorUs1() #0 {575entry:576 %0 = load i16, ptr @us1, align 2, !tbaa !5577 %xor = xor i16 %0, 60024578 store i16 %xor, ptr @us, align 2, !tbaa !5579; CHECK-LABEL: .ent xorUs1580; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)581; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)582; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25583; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])584; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])585; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])586; CHECK-DAG: ori $[[CONST_60024:[0-9]+]], $zero, 60024587; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_60024]]588; CHECK: sh $[[RES]], 0($[[US_ADDR]])589; CHECK: .end xorUs1590 ret void591}592 593attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" }594attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" }595attributes #2 = { nounwind }596 597!llvm.module.flags = !{!0}598!llvm.ident = !{!1}599 600!0 = !{i32 1, !"PIC Level", i32 2}601!1 = !{!"clang version 3.7.0 (trunk)"}602!2 = !{!3, !3, i64 0}603!3 = !{!"omnipotent char", !4, i64 0}604!4 = !{!"Simple C/C++ TBAA"}605!5 = !{!6, !6, i64 0}606!6 = !{!"short", !3, i64 0}607