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1; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -O0 -relocation-model=pic2; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic3 4; The test is just to make sure it is able to allocate5; registers for this example. There was an issue with allocating AC06; after a mul instruction.7 8declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)9 10define i32 @foo(i32 %a, i32 %b) {11entry:12 %0 = mul i32 %a, %b13 %1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %b)14 %2 = extractvalue { i32, i1 } %1, 015 ret i32 %216}17