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1; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -O0 -relocation-model=pic \2; RUN: -fast-isel-abort=3 | FileCheck %s3; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \4; RUN: -fast-isel-abort=3 | FileCheck %s5 6@sj = global i32 200, align 47@sk = global i32 -47, align 48@uj = global i32 200, align 49@uk = global i32 43, align 410@si = common global i32 0, align 411@ui = common global i32 0, align 412 13define void @rems() {14 ; CHECK-LABEL: rems:15 16 ; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)17 ; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)18 ; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $2519 ; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]])20 ; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]])21 ; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]])22 ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])23 ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])24 ; CHECK-DAG: div $zero, $[[J]], $[[K]]25 ; CHECK-DAG: teq $[[K]], $zero, 726 ; CHECK-DAG: mfhi $[[RESULT:[0-9]+]]27 ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])28 %1 = load i32, ptr @sj, align 429 %2 = load i32, ptr @sk, align 430 %rem = srem i32 %1, %231 store i32 %rem, ptr @si, align 432 ret void33}34 35; Function Attrs: noinline nounwind36define void @remu() {37 ; CHECK-LABEL: remu:38 39 ; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)40 ; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)41 ; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $2542 ; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]])43 ; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]])44 ; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]])45 ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])46 ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])47 ; CHECK-DAG: divu $zero, $[[J]], $[[K]]48 ; CHECK-DAG: teq $[[K]], $zero, 749 ; CHECK-DAG: mfhi $[[RESULT:[0-9]+]]50 ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])51 %1 = load i32, ptr @uj, align 452 %2 = load i32, ptr @uk, align 453 %rem = urem i32 %1, %254 store i32 %rem, ptr @ui, align 455 ret void56}57