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1; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \2; RUN: < %s | FileCheck %s3 4@i = global i32 75, align 45@s = global i16 -345, align 26@c = global i8 118, align 17@f = global float 0x40BE623360000000, align 48@d = global double 1.298330e+03, align 89 10; Function Attrs: nounwind11define i32 @reti() {12entry:13; CHECK-LABEL: reti:14 %0 = load i32, ptr @i, align 415 ret i32 %016; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)17; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)18; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $2519; CHECK: lw $[[REG_I_ADDR:[0-9]+]], %got(i)($[[REG_GP]])20; CHECK: lw $2, 0($[[REG_I_ADDR]])21; CHECK: jr $ra22}23 24; Function Attrs: nounwind25define i16 @retus() {26entry:27; CHECK-LABEL: retus:28 %0 = load i16, ptr @s, align 229 ret i16 %030; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)31; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)32; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $2533; CHECK: lw $[[REG_S_ADDR:[0-9]+]], %got(s)($[[REG_GP]])34; CHECK: lhu $2, 0($[[REG_S_ADDR]])35; CHECK: jr $ra36}37 38; Function Attrs: nounwind39define signext i16 @rets() {40entry:41; CHECK-LABEL: rets:42 %0 = load i16, ptr @s, align 243 ret i16 %044; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)45; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)46; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $2547; CHECK: lw $[[REG_S_ADDR:[0-9]+]], %got(s)($[[REG_GP]])48; CHECK: lhu $[[REG_S:[0-9]+]], 0($[[REG_S_ADDR]])49; CHECK: seh $2, $[[REG_S]]50; CHECK: jr $ra51}52 53; Function Attrs: nounwind54define i8 @retuc() {55entry:56; CHECK-LABEL: retuc:57 %0 = load i8, ptr @c, align 158 ret i8 %059; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)60; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)61; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $2562; CHECK: lw $[[REG_C_ADDR:[0-9]+]], %got(c)($[[REG_GP]])63; CHECK: lbu $2, 0($[[REG_C_ADDR]])64; CHECK: jr $ra65}66 67; Function Attrs: nounwind68define signext i8 @retc() {69entry:70; CHECK-LABEL: retc:71 %0 = load i8, ptr @c, align 172 ret i8 %073; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)74; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)75; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $2576; CHECK: lw $[[REG_C_ADDR:[0-9]+]], %got(c)($[[REG_GP]])77; CHECK: lbu $[[REG_C:[0-9]+]], 0($[[REG_C_ADDR]])78; CHECK: seb $2, $[[REG_C]]79; CHECK: jr $ra80}81 82; Function Attrs: nounwind83define float @retf() {84entry:85; CHECK-LABEL: retf:86 %0 = load float, ptr @f, align 487 ret float %088; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)89; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)90; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $2591; CHECK: lw $[[REG_F_ADDR:[0-9]+]], %got(f)($[[REG_GP]])92; CHECK: lwc1 $f0, 0($[[REG_F_ADDR]])93; CHECK: jr $ra94}95 96; Function Attrs: nounwind97define double @retd() {98entry:99; CHECK-LABEL: retd:100 %0 = load double, ptr @d, align 8101 ret double %0102; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)103; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)104; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25105; CHECK: lw $[[REG_D_ADDR:[0-9]+]], %got(d)($[[REG_GP]])106; CHECK: ldc1 $f0, 0($[[REG_D_ADDR]])107; CHECK: jr $ra108}109