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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -O2 -relocation-model=pic \3; RUN: -fast-isel -fast-isel-abort=1 | FileCheck %s4 5; FIXME: The first xor instruction is redundant.6define i1 @sel_i1(i1 %j, i1 %k, i1 %l) {7; CHECK-LABEL: sel_i1:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: xor $1, $4, $zero10; CHECK-NEXT: andi $1, $1, 111; CHECK-NEXT: movn $6, $5, $112; CHECK-NEXT: jr $ra13; CHECK-NEXT: move $2, $614entry:15 %cond = xor i1 %j, false16 %res = select i1 %cond, i1 %k, i1 %l17 ret i1 %res18}19 20; FIXME: The seb $X, $zero and xor .., .., $x instructions are redundant.21define i8 @sel_i8(i8 %j, i8 %k, i8 %l) {22; CHECK-LABEL: sel_i8:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: seb $1, $425; CHECK-NEXT: seb $2, $zero26; CHECK-NEXT: xor $1, $1, $227; CHECK-NEXT: sltu $1, $zero, $128; CHECK-NEXT: andi $1, $1, 129; CHECK-NEXT: movn $6, $5, $130; CHECK-NEXT: jr $ra31; CHECK-NEXT: move $2, $632entry:33 %cond = icmp ne i8 %j, 034 %res = select i1 %cond, i8 %k, i8 %l35 ret i8 %res36}37 38; FIXME: The seh $X, $zero and xor .., .., $x instructions are redundant.39define i16 @sel_i16(i16 %j, i16 %k, i16 %l) {40; CHECK-LABEL: sel_i16:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: seh $1, $443; CHECK-NEXT: seh $2, $zero44; CHECK-NEXT: xor $1, $1, $245; CHECK-NEXT: sltu $1, $zero, $146; CHECK-NEXT: andi $1, $1, 147; CHECK-NEXT: movn $6, $5, $148; CHECK-NEXT: jr $ra49; CHECK-NEXT: move $2, $650entry:51 %cond = icmp ne i16 %j, 052 %res = select i1 %cond, i16 %k, i16 %l53 ret i16 %res54}55 56; FIXME: The first xor instruction is redundant.57define i32 @sel_i32(i32 %j, i32 %k, i32 %l) {58; CHECK-LABEL: sel_i32:59; CHECK: # %bb.0: # %entry60; CHECK-NEXT: xor $1, $4, $zero61; CHECK-NEXT: sltu $1, $zero, $162; CHECK-NEXT: andi $1, $1, 163; CHECK-NEXT: movn $6, $5, $164; CHECK-NEXT: jr $ra65; CHECK-NEXT: move $2, $666entry:67 %cond = icmp ne i32 %j, 068 %res = select i1 %cond, i32 %k, i32 %l69 ret i32 %res70}71 72define float @sel_float(i32 %j, float %k, float %l) {73; CHECK-LABEL: sel_float:74; CHECK: # %bb.0: # %entry75; CHECK-NEXT: mtc1 $6, $f076; CHECK-NEXT: mtc1 $5, $f177; CHECK-NEXT: xor $1, $4, $zero78; CHECK-NEXT: sltu $1, $zero, $179; CHECK-NEXT: andi $1, $1, 180; CHECK-NEXT: jr $ra81; CHECK-NEXT: movn.s $f0, $f1, $182entry:83 %cond = icmp ne i32 %j, 084 %res = select i1 %cond, float %k, float %l85 ret float %res86}87 88define float @sel_float2(float %k, float %l, i32 %j) {89; CHECK-LABEL: sel_float2:90; CHECK: # %bb.0: # %entry91; CHECK-NEXT: mov.s $f0, $f1492; CHECK-NEXT: xor $1, $6, $zero93; CHECK-NEXT: sltu $1, $zero, $194; CHECK-NEXT: andi $1, $1, 195; CHECK-NEXT: jr $ra96; CHECK-NEXT: movn.s $f0, $f12, $197entry:98 %cond = icmp ne i32 %j, 099 %res = select i1 %cond, float %k, float %l100 ret float %res101}102 103define double @sel_double(i32 %j, double %k, double %l) {104; CHECK-LABEL: sel_double:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: mtc1 $6, $f2107; CHECK-NEXT: mthc1 $7, $f2108; CHECK-NEXT: ldc1 $f0, 16($sp)109; CHECK-NEXT: xor $1, $4, $zero110; CHECK-NEXT: sltu $1, $zero, $1111; CHECK-NEXT: andi $1, $1, 1112; CHECK-NEXT: jr $ra113; CHECK-NEXT: movn.d $f0, $f2, $1114entry:115 %cond = icmp ne i32 %j, 0116 %res = select i1 %cond, double %k, double %l117 ret double %res118}119 120define double @sel_double2(double %k, double %l, i32 %j) {121; CHECK-LABEL: sel_double2:122; CHECK: # %bb.0: # %entry123; CHECK-NEXT: mov.d $f0, $f14124; CHECK-NEXT: lw $1, 16($sp)125; CHECK-NEXT: xor $1, $1, $zero126; CHECK-NEXT: sltu $1, $zero, $1127; CHECK-NEXT: andi $1, $1, 1128; CHECK-NEXT: jr $ra129; CHECK-NEXT: movn.d $f0, $f12, $1130entry:131 %cond = icmp ne i32 %j, 0132 %res = select i1 %cond, double %k, double %l133 ret double %res134}135