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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -march mips -fast-isel -relocation-model pic | FileCheck %s -check-prefixes=MIPS-323; RUN: llc < %s -march mips64 -fast-isel -relocation-model pic | FileCheck %s -check-prefixes=MIPS-644; RUN: llc < %s -march mips -mcpu mips32r6 -fast-isel -relocation-model pic | FileCheck %s -check-prefixes=MIPS-32-R65; RUN: llc < %s -march mips -mcpu mips32r6 -mattr +strict-align -fast-isel -relocation-model pic | FileCheck %s -check-prefixes=MIPS-32-R6-STRICT6; RUN: llc < %s -march mips64 -mcpu mips64r6 -fast-isel -relocation-model pic | FileCheck %s -check-prefixes=MIPS-64-R67; RUN: llc < %s -march mips64 -mcpu mips64r6 -mattr +strict-align -fast-isel -relocation-model pic | FileCheck %s -check-prefixes=MIPS-64-R6-STRICT8 9@var = external global i32, align 110 11; FastISel should bail on the underaligned load and store, except on r6 with non-strict alignment.12define dso_local ccc i32 @__start() {13; MIPS-32-LABEL: __start:14; MIPS-32: # %bb.0:15; MIPS-32-NEXT: lui $2, %hi(_gp_disp)16; MIPS-32-NEXT: addiu $2, $2, %lo(_gp_disp)17; MIPS-32-NEXT: addu $1, $2, $2518; MIPS-32-NEXT: lw $1, %got(var)($1)19; MIPS-32-NEXT: lwl $2, 0($1)20; MIPS-32-NEXT: lwr $2, 3($1)21; MIPS-32-NEXT: addiu $3, $zero, 4222; MIPS-32-NEXT: swl $3, 0($1)23; MIPS-32-NEXT: jr $ra24; MIPS-32-NEXT: swr $3, 3($1)25;26; MIPS-64-LABEL: __start:27; MIPS-64: # %bb.0:28; MIPS-64-NEXT: lui $1, %hi(%neg(%gp_rel(__start)))29; MIPS-64-NEXT: daddu $1, $1, $2530; MIPS-64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(__start)))31; MIPS-64-NEXT: ld $1, %got_disp(var)($1)32; MIPS-64-NEXT: lwl $2, 0($1)33; MIPS-64-NEXT: lwr $2, 3($1)34; MIPS-64-NEXT: addiu $3, $zero, 4235; MIPS-64-NEXT: swl $3, 0($1)36; MIPS-64-NEXT: jr $ra37; MIPS-64-NEXT: swr $3, 3($1)38;39; MIPS-32-R6-LABEL: __start:40; MIPS-32-R6: # %bb.0:41; MIPS-32-R6-NEXT: lui $2, %hi(_gp_disp)42; MIPS-32-R6-NEXT: addiu $2, $2, %lo(_gp_disp)43; MIPS-32-R6-NEXT: addu $1, $2, $2544; MIPS-32-R6-NEXT: lw $1, %got(var)($1)45; MIPS-32-R6-NEXT: lw $2, 0($1)46; MIPS-32-R6-NEXT: addiu $3, $zero, 4247; MIPS-32-R6-NEXT: jr $ra48; MIPS-32-R6-NEXT: sw $3, 0($1)49;50; MIPS-32-R6-STRICT-LABEL: __start:51; MIPS-32-R6-STRICT: # %bb.0:52; MIPS-32-R6-STRICT-NEXT: lui $2, %hi(_gp_disp)53; MIPS-32-R6-STRICT-NEXT: addiu $2, $2, %lo(_gp_disp)54; MIPS-32-R6-STRICT-NEXT: addu $1, $2, $2555; MIPS-32-R6-STRICT-NEXT: lw $1, %got(var)($1)56; MIPS-32-R6-STRICT-NEXT: lbu $2, 0($1)57; MIPS-32-R6-STRICT-NEXT: lbu $3, 1($1)58; MIPS-32-R6-STRICT-NEXT: lbu $4, 3($1)59; MIPS-32-R6-STRICT-NEXT: lbu $5, 2($1)60; MIPS-32-R6-STRICT-NEXT: addiu $6, $zero, 4261; MIPS-32-R6-STRICT-NEXT: sb $zero, 2($1)62; MIPS-32-R6-STRICT-NEXT: sb $6, 3($1)63; MIPS-32-R6-STRICT-NEXT: sb $zero, 0($1)64; MIPS-32-R6-STRICT-NEXT: sb $zero, 1($1)65; MIPS-32-R6-STRICT-NEXT: sll $1, $5, 866; MIPS-32-R6-STRICT-NEXT: or $1, $1, $467; MIPS-32-R6-STRICT-NEXT: sll $3, $3, 1668; MIPS-32-R6-STRICT-NEXT: sll $2, $2, 2469; MIPS-32-R6-STRICT-NEXT: or $2, $2, $370; MIPS-32-R6-STRICT-NEXT: jr $ra71; MIPS-32-R6-STRICT-NEXT: or $2, $2, $172;73; MIPS-64-R6-LABEL: __start:74; MIPS-64-R6: # %bb.0:75; MIPS-64-R6-NEXT: lui $1, %hi(%neg(%gp_rel(__start)))76; MIPS-64-R6-NEXT: daddu $1, $1, $2577; MIPS-64-R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(__start)))78; MIPS-64-R6-NEXT: ld $1, %got_disp(var)($1)79; MIPS-64-R6-NEXT: lw $2, 0($1)80; MIPS-64-R6-NEXT: addiu $3, $zero, 4281; MIPS-64-R6-NEXT: jr $ra82; MIPS-64-R6-NEXT: sw $3, 0($1)83;84; MIPS-64-R6-STRICT-LABEL: __start:85; MIPS-64-R6-STRICT: # %bb.0:86; MIPS-64-R6-STRICT-NEXT: lui $1, %hi(%neg(%gp_rel(__start)))87; MIPS-64-R6-STRICT-NEXT: daddu $1, $1, $2588; MIPS-64-R6-STRICT-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(__start)))89; MIPS-64-R6-STRICT-NEXT: ld $1, %got_disp(var)($1)90; MIPS-64-R6-STRICT-NEXT: lbu $2, 0($1)91; MIPS-64-R6-STRICT-NEXT: lbu $3, 1($1)92; MIPS-64-R6-STRICT-NEXT: lbu $4, 3($1)93; MIPS-64-R6-STRICT-NEXT: lbu $5, 2($1)94; MIPS-64-R6-STRICT-NEXT: addiu $6, $zero, 4295; MIPS-64-R6-STRICT-NEXT: sb $zero, 2($1)96; MIPS-64-R6-STRICT-NEXT: sb $6, 3($1)97; MIPS-64-R6-STRICT-NEXT: sb $zero, 0($1)98; MIPS-64-R6-STRICT-NEXT: sb $zero, 1($1)99; MIPS-64-R6-STRICT-NEXT: sll $1, $5, 8100; MIPS-64-R6-STRICT-NEXT: or $1, $1, $4101; MIPS-64-R6-STRICT-NEXT: sll $3, $3, 16102; MIPS-64-R6-STRICT-NEXT: sll $2, $2, 24103; MIPS-64-R6-STRICT-NEXT: or $2, $2, $3104; MIPS-64-R6-STRICT-NEXT: jr $ra105; MIPS-64-R6-STRICT-NEXT: or $2, $2, $1106 %1 = load i32, ptr @var, align 1107 store i32 42, ptr @var, align 1108 ret i32 %1109}110