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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P56003--- |4 5 define void @add_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }6 define void @add_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }7 define void @add_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }8 define void @add_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }9 10...11---12name: add_v16i813alignment: 414legalized: true15regBankSelected: true16tracksRegLiveness: true17body: |18 bb.1.entry:19 liveins: $a0, $a1, $a220 21 ; P5600-LABEL: name: add_v16i822 ; P5600: liveins: $a0, $a1, $a223 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a024 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a125 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a226 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)27 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)28 ; P5600: [[ADDV_B:%[0-9]+]]:msa128b = ADDV_B [[LD_B1]], [[LD_B]]29 ; P5600: ST_B [[ADDV_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)30 ; P5600: RetRA31 %0:gprb(p0) = COPY $a032 %1:gprb(p0) = COPY $a133 %2:gprb(p0) = COPY $a234 %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)35 %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)36 %5:fprb(<16 x s8>) = G_ADD %4, %337 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)38 RetRA39 40...41---42name: add_v8i1643alignment: 444legalized: true45regBankSelected: true46tracksRegLiveness: true47body: |48 bb.1.entry:49 liveins: $a0, $a1, $a250 51 ; P5600-LABEL: name: add_v8i1652 ; P5600: liveins: $a0, $a1, $a253 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a054 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a155 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a256 ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)57 ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)58 ; P5600: [[ADDV_H:%[0-9]+]]:msa128h = ADDV_H [[LD_H1]], [[LD_H]]59 ; P5600: ST_H [[ADDV_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)60 ; P5600: RetRA61 %0:gprb(p0) = COPY $a062 %1:gprb(p0) = COPY $a163 %2:gprb(p0) = COPY $a264 %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)65 %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)66 %5:fprb(<8 x s16>) = G_ADD %4, %367 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)68 RetRA69 70...71---72name: add_v4i3273alignment: 474legalized: true75regBankSelected: true76tracksRegLiveness: true77body: |78 bb.1.entry:79 liveins: $a0, $a1, $a280 81 ; P5600-LABEL: name: add_v4i3282 ; P5600: liveins: $a0, $a1, $a283 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a084 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a185 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a286 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)87 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)88 ; P5600: [[ADDV_W:%[0-9]+]]:msa128w = ADDV_W [[LD_W1]], [[LD_W]]89 ; P5600: ST_W [[ADDV_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)90 ; P5600: RetRA91 %0:gprb(p0) = COPY $a092 %1:gprb(p0) = COPY $a193 %2:gprb(p0) = COPY $a294 %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)95 %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)96 %5:fprb(<4 x s32>) = G_ADD %4, %397 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)98 RetRA99 100...101---102name: add_v2i64103alignment: 4104legalized: true105regBankSelected: true106tracksRegLiveness: true107body: |108 bb.1.entry:109 liveins: $a0, $a1, $a2110 111 ; P5600-LABEL: name: add_v2i64112 ; P5600: liveins: $a0, $a1, $a2113 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0114 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1115 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2116 ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)117 ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)118 ; P5600: [[ADDV_D:%[0-9]+]]:msa128d = ADDV_D [[LD_D1]], [[LD_D]]119 ; P5600: ST_D [[ADDV_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)120 ; P5600: RetRA121 %0:gprb(p0) = COPY $a0122 %1:gprb(p0) = COPY $a1123 %2:gprb(p0) = COPY $a2124 %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)125 %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)126 %5:fprb(<2 x s64>) = G_ADD %4, %3127 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)128 RetRA129 130...131