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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP323# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP644--- |5 6 define void @float_add() {entry: ret void}7 define void @float_sub() {entry: ret void}8 define void @float_mul() {entry: ret void}9 define void @float_div() {entry: ret void}10 define void @double_add() {entry: ret void}11 define void @double_sub() {entry: ret void}12 define void @double_mul() {entry: ret void}13 define void @double_div() {entry: ret void}14 15...16---17name: float_add18alignment: 419legalized: true20regBankSelected: true21tracksRegLiveness: true22body: |23 bb.1.entry:24 liveins: $f12, $f1425 26 ; FP32-LABEL: name: float_add27 ; FP32: liveins: $f12, $f1428 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f1229 ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f1430 ; FP32: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]31 ; FP32: $f0 = COPY [[FADD_S]]32 ; FP32: RetRA implicit $f033 ; FP64-LABEL: name: float_add34 ; FP64: liveins: $f12, $f1435 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f1236 ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f1437 ; FP64: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]38 ; FP64: $f0 = COPY [[FADD_S]]39 ; FP64: RetRA implicit $f040 %0:fprb(s32) = COPY $f1241 %1:fprb(s32) = COPY $f1442 %2:fprb(s32) = G_FADD %0, %143 $f0 = COPY %2(s32)44 RetRA implicit $f045 46...47---48name: float_sub49alignment: 450legalized: true51regBankSelected: true52tracksRegLiveness: true53body: |54 bb.1.entry:55 liveins: $f12, $f1456 57 ; FP32-LABEL: name: float_sub58 ; FP32: liveins: $f12, $f1459 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f1260 ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f1461 ; FP32: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]62 ; FP32: $f0 = COPY [[FSUB_S]]63 ; FP32: RetRA implicit $f064 ; FP64-LABEL: name: float_sub65 ; FP64: liveins: $f12, $f1466 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f1267 ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f1468 ; FP64: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]69 ; FP64: $f0 = COPY [[FSUB_S]]70 ; FP64: RetRA implicit $f071 %0:fprb(s32) = COPY $f1272 %1:fprb(s32) = COPY $f1473 %2:fprb(s32) = G_FSUB %0, %174 $f0 = COPY %2(s32)75 RetRA implicit $f076 77...78---79name: float_mul80alignment: 481legalized: true82regBankSelected: true83tracksRegLiveness: true84body: |85 bb.1.entry:86 liveins: $f12, $f1487 88 ; FP32-LABEL: name: float_mul89 ; FP32: liveins: $f12, $f1490 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f1291 ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f1492 ; FP32: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]93 ; FP32: $f0 = COPY [[FMUL_S]]94 ; FP32: RetRA implicit $f095 ; FP64-LABEL: name: float_mul96 ; FP64: liveins: $f12, $f1497 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f1298 ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f1499 ; FP64: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]100 ; FP64: $f0 = COPY [[FMUL_S]]101 ; FP64: RetRA implicit $f0102 %0:fprb(s32) = COPY $f12103 %1:fprb(s32) = COPY $f14104 %2:fprb(s32) = G_FMUL %0, %1105 $f0 = COPY %2(s32)106 RetRA implicit $f0107 108...109---110name: float_div111alignment: 4112legalized: true113regBankSelected: true114tracksRegLiveness: true115body: |116 bb.1.entry:117 liveins: $f12, $f14118 119 ; FP32-LABEL: name: float_div120 ; FP32: liveins: $f12, $f14121 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12122 ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14123 ; FP32: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]124 ; FP32: $f0 = COPY [[FDIV_S]]125 ; FP32: RetRA implicit $f0126 ; FP64-LABEL: name: float_div127 ; FP64: liveins: $f12, $f14128 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12129 ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14130 ; FP64: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]131 ; FP64: $f0 = COPY [[FDIV_S]]132 ; FP64: RetRA implicit $f0133 %0:fprb(s32) = COPY $f12134 %1:fprb(s32) = COPY $f14135 %2:fprb(s32) = G_FDIV %0, %1136 $f0 = COPY %2(s32)137 RetRA implicit $f0138 139...140---141name: double_add142alignment: 4143legalized: true144regBankSelected: true145tracksRegLiveness: true146body: |147 bb.1.entry:148 liveins: $d6, $d7149 150 ; FP32-LABEL: name: double_add151 ; FP32: liveins: $d6, $d7152 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6153 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7154 ; FP32: [[FADD_D32_:%[0-9]+]]:afgr64 = FADD_D32 [[COPY]], [[COPY1]]155 ; FP32: $d0 = COPY [[FADD_D32_]]156 ; FP32: RetRA implicit $d0157 ; FP64-LABEL: name: double_add158 ; FP64: liveins: $d6, $d7159 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6160 ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7161 ; FP64: [[FADD_D64_:%[0-9]+]]:fgr64 = FADD_D64 [[COPY]], [[COPY1]]162 ; FP64: $d0 = COPY [[FADD_D64_]]163 ; FP64: RetRA implicit $d0164 %0:fprb(s64) = COPY $d6165 %1:fprb(s64) = COPY $d7166 %2:fprb(s64) = G_FADD %0, %1167 $d0 = COPY %2(s64)168 RetRA implicit $d0169 170...171---172name: double_sub173alignment: 4174legalized: true175regBankSelected: true176tracksRegLiveness: true177body: |178 bb.1.entry:179 liveins: $d6, $d7180 181 ; FP32-LABEL: name: double_sub182 ; FP32: liveins: $d6, $d7183 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6184 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7185 ; FP32: [[FSUB_D32_:%[0-9]+]]:afgr64 = FSUB_D32 [[COPY]], [[COPY1]]186 ; FP32: $d0 = COPY [[FSUB_D32_]]187 ; FP32: RetRA implicit $d0188 ; FP64-LABEL: name: double_sub189 ; FP64: liveins: $d6, $d7190 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6191 ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7192 ; FP64: [[FSUB_D64_:%[0-9]+]]:fgr64 = FSUB_D64 [[COPY]], [[COPY1]]193 ; FP64: $d0 = COPY [[FSUB_D64_]]194 ; FP64: RetRA implicit $d0195 %0:fprb(s64) = COPY $d6196 %1:fprb(s64) = COPY $d7197 %2:fprb(s64) = G_FSUB %0, %1198 $d0 = COPY %2(s64)199 RetRA implicit $d0200 201...202---203name: double_mul204alignment: 4205legalized: true206regBankSelected: true207tracksRegLiveness: true208body: |209 bb.1.entry:210 liveins: $d6, $d7211 212 ; FP32-LABEL: name: double_mul213 ; FP32: liveins: $d6, $d7214 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6215 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7216 ; FP32: [[FMUL_D32_:%[0-9]+]]:afgr64 = FMUL_D32 [[COPY]], [[COPY1]]217 ; FP32: $d0 = COPY [[FMUL_D32_]]218 ; FP32: RetRA implicit $d0219 ; FP64-LABEL: name: double_mul220 ; FP64: liveins: $d6, $d7221 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6222 ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7223 ; FP64: [[FMUL_D64_:%[0-9]+]]:fgr64 = FMUL_D64 [[COPY]], [[COPY1]]224 ; FP64: $d0 = COPY [[FMUL_D64_]]225 ; FP64: RetRA implicit $d0226 %0:fprb(s64) = COPY $d6227 %1:fprb(s64) = COPY $d7228 %2:fprb(s64) = G_FMUL %0, %1229 $d0 = COPY %2(s64)230 RetRA implicit $d0231 232...233---234name: double_div235alignment: 4236legalized: true237regBankSelected: true238tracksRegLiveness: true239body: |240 bb.1.entry:241 liveins: $d6, $d7242 243 ; FP32-LABEL: name: double_div244 ; FP32: liveins: $d6, $d7245 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6246 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7247 ; FP32: [[FDIV_D32_:%[0-9]+]]:afgr64 = FDIV_D32 [[COPY]], [[COPY1]]248 ; FP32: $d0 = COPY [[FDIV_D32_]]249 ; FP32: RetRA implicit $d0250 ; FP64-LABEL: name: double_div251 ; FP64: liveins: $d6, $d7252 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6253 ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7254 ; FP64: [[FDIV_D64_:%[0-9]+]]:fgr64 = FDIV_D64 [[COPY]], [[COPY1]]255 ; FP64: $d0 = COPY [[FDIV_D64_]]256 ; FP64: RetRA implicit $d0257 %0:fprb(s64) = COPY $d6258 %1:fprb(s64) = COPY $d7259 %2:fprb(s64) = G_FDIV %0, %1260 $d0 = COPY %2(s64)261 RetRA implicit $d0262 263...264