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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS323# RUN: llc -O0 -mtriple=mipsel-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32_PIC4--- |5 6 define i32 @mod4_0_to_11(i32 %a) {7 entry:8 switch i32 %a, label %sw.default [9 i32 0, label %sw.bb10 i32 4, label %sw.bb11 i32 1, label %sw.bb112 i32 5, label %sw.bb113 i32 2, label %sw.bb214 i32 6, label %sw.bb215 i32 3, label %sw.bb316 i32 7, label %sw.bb317 ]18 19 sw.bb: ; preds = %entry, %entry20 ret i32 021 22 sw.bb1: ; preds = %entry, %entry23 ret i32 124 25 sw.bb2: ; preds = %entry, %entry26 ret i32 227 28 sw.bb3: ; preds = %entry, %entry29 ret i32 330 31 sw.default: ; preds = %entry32 br label %sw.epilog33 34 sw.epilog: ; preds = %sw.default35 switch i32 %a, label %sw.default8 [36 i32 8, label %sw.bb437 i32 9, label %sw.bb538 i32 10, label %sw.bb639 i32 11, label %sw.bb740 ]41 42 sw.bb4: ; preds = %sw.epilog43 ret i32 044 45 sw.bb5: ; preds = %sw.epilog46 ret i32 147 48 sw.bb6: ; preds = %sw.epilog49 ret i32 250 51 sw.bb7: ; preds = %sw.epilog52 ret i32 353 54 sw.default8: ; preds = %sw.epilog55 ret i32 -156 }57 58...59---60name: mod4_0_to_1161alignment: 462legalized: true63regBankSelected: true64tracksRegLiveness: true65jumpTable:66 kind: block-address67 entries:68 - id: 069 blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.2', '%bb.3',70 '%bb.4', '%bb.5' ]71 - id: 172 blocks: [ '%bb.8', '%bb.9', '%bb.10', '%bb.11' ]73body: |74 ; MIPS32-LABEL: name: mod4_0_to_1175 ; MIPS32: bb.0.entry:76 ; MIPS32-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)77 ; MIPS32-NEXT: liveins: $a078 ; MIPS32-NEXT: {{ $}}79 ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a080 ; MIPS32-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 781 ; MIPS32-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 382 ; MIPS32-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 283 ; MIPS32-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 184 ; MIPS32-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 085 ; MIPS32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 6553586 ; MIPS32-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 087 ; MIPS32-NEXT: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]88 ; MIPS32-NEXT: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]89 ; MIPS32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 190 ; MIPS32-NEXT: BNE [[ANDi]], $zero, %bb.6, implicit-def dead $at91 ; MIPS32-NEXT: {{ $}}92 ; MIPS32-NEXT: bb.1.entry:93 ; MIPS32-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)94 ; MIPS32-NEXT: {{ $}}95 ; MIPS32-NEXT: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.096 ; MIPS32-NEXT: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 297 ; MIPS32-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[SLL]]98 ; MIPS32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))99 ; MIPS32-NEXT: PseudoIndirectBranch [[LW]]100 ; MIPS32-NEXT: {{ $}}101 ; MIPS32-NEXT: bb.2.sw.bb:102 ; MIPS32-NEXT: $v0 = COPY [[ORi4]]103 ; MIPS32-NEXT: RetRA implicit $v0104 ; MIPS32-NEXT: {{ $}}105 ; MIPS32-NEXT: bb.3.sw.bb1:106 ; MIPS32-NEXT: $v0 = COPY [[ORi3]]107 ; MIPS32-NEXT: RetRA implicit $v0108 ; MIPS32-NEXT: {{ $}}109 ; MIPS32-NEXT: bb.4.sw.bb2:110 ; MIPS32-NEXT: $v0 = COPY [[ORi2]]111 ; MIPS32-NEXT: RetRA implicit $v0112 ; MIPS32-NEXT: {{ $}}113 ; MIPS32-NEXT: bb.5.sw.bb3:114 ; MIPS32-NEXT: $v0 = COPY [[ORi1]]115 ; MIPS32-NEXT: RetRA implicit $v0116 ; MIPS32-NEXT: {{ $}}117 ; MIPS32-NEXT: bb.6.sw.default:118 ; MIPS32-NEXT: successors: %bb.7(0x80000000)119 ; MIPS32-NEXT: {{ $}}120 ; MIPS32-NEXT: bb.7.sw.epilog:121 ; MIPS32-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000)122 ; MIPS32-NEXT: {{ $}}123 ; MIPS32-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8124 ; MIPS32-NEXT: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]125 ; MIPS32-NEXT: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]126 ; MIPS32-NEXT: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1127 ; MIPS32-NEXT: BNE [[ANDi1]], $zero, %bb.13, implicit-def dead $at128 ; MIPS32-NEXT: {{ $}}129 ; MIPS32-NEXT: bb.8.sw.epilog:130 ; MIPS32-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)131 ; MIPS32-NEXT: {{ $}}132 ; MIPS32-NEXT: [[LUi1:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.1133 ; MIPS32-NEXT: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2134 ; MIPS32-NEXT: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi1]], [[SLL1]]135 ; MIPS32-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))136 ; MIPS32-NEXT: PseudoIndirectBranch [[LW1]]137 ; MIPS32-NEXT: {{ $}}138 ; MIPS32-NEXT: bb.9.sw.bb4:139 ; MIPS32-NEXT: $v0 = COPY [[ORi4]]140 ; MIPS32-NEXT: RetRA implicit $v0141 ; MIPS32-NEXT: {{ $}}142 ; MIPS32-NEXT: bb.10.sw.bb5:143 ; MIPS32-NEXT: $v0 = COPY [[ORi3]]144 ; MIPS32-NEXT: RetRA implicit $v0145 ; MIPS32-NEXT: {{ $}}146 ; MIPS32-NEXT: bb.11.sw.bb6:147 ; MIPS32-NEXT: $v0 = COPY [[ORi2]]148 ; MIPS32-NEXT: RetRA implicit $v0149 ; MIPS32-NEXT: {{ $}}150 ; MIPS32-NEXT: bb.12.sw.bb7:151 ; MIPS32-NEXT: $v0 = COPY [[ORi1]]152 ; MIPS32-NEXT: RetRA implicit $v0153 ; MIPS32-NEXT: {{ $}}154 ; MIPS32-NEXT: bb.13.sw.default8:155 ; MIPS32-NEXT: $v0 = COPY [[ADDiu]]156 ; MIPS32-NEXT: RetRA implicit $v0157 ;158 ; MIPS32_PIC-LABEL: name: mod4_0_to_11159 ; MIPS32_PIC: bb.0.entry:160 ; MIPS32_PIC-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)161 ; MIPS32_PIC-NEXT: liveins: $a0, $t9, $v0162 ; MIPS32_PIC-NEXT: {{ $}}163 ; MIPS32_PIC-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9164 ; MIPS32_PIC-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0165 ; MIPS32_PIC-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7166 ; MIPS32_PIC-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3167 ; MIPS32_PIC-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2168 ; MIPS32_PIC-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1169 ; MIPS32_PIC-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0170 ; MIPS32_PIC-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535171 ; MIPS32_PIC-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0172 ; MIPS32_PIC-NEXT: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]173 ; MIPS32_PIC-NEXT: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]174 ; MIPS32_PIC-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1175 ; MIPS32_PIC-NEXT: BNE [[ANDi]], $zero, %bb.6, implicit-def dead $at176 ; MIPS32_PIC-NEXT: {{ $}}177 ; MIPS32_PIC-NEXT: bb.1.entry:178 ; MIPS32_PIC-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)179 ; MIPS32_PIC-NEXT: {{ $}}180 ; MIPS32_PIC-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.0 :: (load (s32) from got)181 ; MIPS32_PIC-NEXT: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2182 ; MIPS32_PIC-NEXT: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LW]], [[SLL]]183 ; MIPS32_PIC-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))184 ; MIPS32_PIC-NEXT: [[ADDu2:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ADDu]]185 ; MIPS32_PIC-NEXT: PseudoIndirectBranch [[ADDu2]]186 ; MIPS32_PIC-NEXT: {{ $}}187 ; MIPS32_PIC-NEXT: bb.2.sw.bb:188 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi4]]189 ; MIPS32_PIC-NEXT: RetRA implicit $v0190 ; MIPS32_PIC-NEXT: {{ $}}191 ; MIPS32_PIC-NEXT: bb.3.sw.bb1:192 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi3]]193 ; MIPS32_PIC-NEXT: RetRA implicit $v0194 ; MIPS32_PIC-NEXT: {{ $}}195 ; MIPS32_PIC-NEXT: bb.4.sw.bb2:196 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi2]]197 ; MIPS32_PIC-NEXT: RetRA implicit $v0198 ; MIPS32_PIC-NEXT: {{ $}}199 ; MIPS32_PIC-NEXT: bb.5.sw.bb3:200 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi1]]201 ; MIPS32_PIC-NEXT: RetRA implicit $v0202 ; MIPS32_PIC-NEXT: {{ $}}203 ; MIPS32_PIC-NEXT: bb.6.sw.default:204 ; MIPS32_PIC-NEXT: successors: %bb.7(0x80000000)205 ; MIPS32_PIC-NEXT: {{ $}}206 ; MIPS32_PIC-NEXT: bb.7.sw.epilog:207 ; MIPS32_PIC-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000)208 ; MIPS32_PIC-NEXT: {{ $}}209 ; MIPS32_PIC-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8210 ; MIPS32_PIC-NEXT: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]211 ; MIPS32_PIC-NEXT: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]212 ; MIPS32_PIC-NEXT: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1213 ; MIPS32_PIC-NEXT: BNE [[ANDi1]], $zero, %bb.13, implicit-def dead $at214 ; MIPS32_PIC-NEXT: {{ $}}215 ; MIPS32_PIC-NEXT: bb.8.sw.epilog:216 ; MIPS32_PIC-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)217 ; MIPS32_PIC-NEXT: {{ $}}218 ; MIPS32_PIC-NEXT: [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.1 :: (load (s32) from got)219 ; MIPS32_PIC-NEXT: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2220 ; MIPS32_PIC-NEXT: [[ADDu3:%[0-9]+]]:gpr32 = ADDu [[LW2]], [[SLL1]]221 ; MIPS32_PIC-NEXT: [[LW3:%[0-9]+]]:gpr32 = LW [[ADDu3]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))222 ; MIPS32_PIC-NEXT: [[ADDu4:%[0-9]+]]:gpr32 = ADDu [[LW3]], [[ADDu]]223 ; MIPS32_PIC-NEXT: PseudoIndirectBranch [[ADDu4]]224 ; MIPS32_PIC-NEXT: {{ $}}225 ; MIPS32_PIC-NEXT: bb.9.sw.bb4:226 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi4]]227 ; MIPS32_PIC-NEXT: RetRA implicit $v0228 ; MIPS32_PIC-NEXT: {{ $}}229 ; MIPS32_PIC-NEXT: bb.10.sw.bb5:230 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi3]]231 ; MIPS32_PIC-NEXT: RetRA implicit $v0232 ; MIPS32_PIC-NEXT: {{ $}}233 ; MIPS32_PIC-NEXT: bb.11.sw.bb6:234 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi2]]235 ; MIPS32_PIC-NEXT: RetRA implicit $v0236 ; MIPS32_PIC-NEXT: {{ $}}237 ; MIPS32_PIC-NEXT: bb.12.sw.bb7:238 ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi1]]239 ; MIPS32_PIC-NEXT: RetRA implicit $v0240 ; MIPS32_PIC-NEXT: {{ $}}241 ; MIPS32_PIC-NEXT: bb.13.sw.default8:242 ; MIPS32_PIC-NEXT: $v0 = COPY [[ADDiu]]243 ; MIPS32_PIC-NEXT: RetRA implicit $v0244 bb.1.entry:245 liveins: $a0246 247 %0:gprb(s32) = COPY $a0248 %4:gprb(s32) = G_CONSTANT i32 7249 %8:gprb(s32) = G_CONSTANT i32 3250 %9:gprb(s32) = G_CONSTANT i32 2251 %10:gprb(s32) = G_CONSTANT i32 1252 %11:gprb(s32) = G_CONSTANT i32 0253 %18:gprb(s32) = G_CONSTANT i32 -1254 %1:gprb(s32) = G_CONSTANT i32 0255 %2:gprb(s32) = G_SUB %0, %1256 %3:gprb(s32) = COPY %2(s32)257 %5:gprb(s32) = COPY %4(s32)258 %22:gprb(s32) = G_ICMP intpred(ugt), %3(s32), %5259 %23:gprb(s32) = COPY %22(s32)260 %21:gprb(s32) = G_AND %23, %10261 G_BRCOND %21(s32), %bb.6262 263 bb.13.entry:264 successors: %bb.2, %bb.3, %bb.4, %bb.5265 266 %7:gprb(p0) = G_JUMP_TABLE %jump-table.0267 G_BRJT %7(p0), %jump-table.0, %3(s32)268 269 bb.2.sw.bb:270 $v0 = COPY %11(s32)271 RetRA implicit $v0272 273 bb.3.sw.bb1:274 $v0 = COPY %10(s32)275 RetRA implicit $v0276 277 bb.4.sw.bb2:278 $v0 = COPY %9(s32)279 RetRA implicit $v0280 281 bb.5.sw.bb3:282 $v0 = COPY %8(s32)283 RetRA implicit $v0284 285 bb.6.sw.default:286 287 bb.7.sw.epilog:288 %12:gprb(s32) = G_CONSTANT i32 8289 %13:gprb(s32) = G_SUB %0, %12290 %14:gprb(s32) = COPY %13(s32)291 %15:gprb(s32) = COPY %8(s32)292 %20:gprb(s32) = G_ICMP intpred(ugt), %14(s32), %15293 %24:gprb(s32) = G_CONSTANT i32 1294 %25:gprb(s32) = COPY %20(s32)295 %19:gprb(s32) = G_AND %25, %24296 G_BRCOND %19(s32), %bb.12297 298 bb.14.sw.epilog:299 successors: %bb.8, %bb.9, %bb.10, %bb.11300 301 %17:gprb(p0) = G_JUMP_TABLE %jump-table.1302 G_BRJT %17(p0), %jump-table.1, %14(s32)303 304 bb.8.sw.bb4:305 $v0 = COPY %11(s32)306 RetRA implicit $v0307 308 bb.9.sw.bb5:309 $v0 = COPY %10(s32)310 RetRA implicit $v0311 312 bb.10.sw.bb6:313 $v0 = COPY %9(s32)314 RetRA implicit $v0315 316 bb.11.sw.bb7:317 $v0 = COPY %8(s32)318 RetRA implicit $v0319 320 bb.12.sw.default8:321 $v0 = COPY %18(s32)322 RetRA implicit $v0323 324...325