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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS323--- |4 5 @float_align1 = common global float 0.000000e+00, align 16 @float_align4 = common global float 0.000000e+00, align 47 @i32_align8 = common global i32 0, align 88 9 define float @load_float_align1() {10 entry:11 %0 = load float, ptr @float_align1, align 112 ret float %013 }14 15 define float @load_float_align4() {16 entry:17 %0 = load float, ptr @float_align4, align 418 ret float %019 }20 21 define i32 @load_i32_align8() {22 entry:23 %0 = load i32, ptr @i32_align8, align 824 ret i32 %025 }26 27...28---29name: load_float_align130alignment: 431legalized: true32regBankSelected: true33tracksRegLiveness: true34body: |35 bb.1.entry:36 ; MIPS32-LABEL: name: load_float_align137 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align138 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align139 ; MIPS32: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF40 ; MIPS32: [[LWL:%[0-9]+]]:gpr32 = LWL [[ADDiu]], 3, [[DEF]] :: (dereferenceable load (s32) from @float_align1, align 1)41 ; MIPS32: [[LWR:%[0-9]+]]:gpr32 = LWR [[ADDiu]], 0, [[LWL]] :: (dereferenceable load (s32) from @float_align1, align 1)42 ; MIPS32: $f0 = COPY [[LWR]]43 ; MIPS32: RetRA implicit $f044 %1:gprb(p0) = G_GLOBAL_VALUE @float_align145 %0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @float_align1, align 1)46 $f0 = COPY %0(s32)47 RetRA implicit $f048 49...50---51name: load_float_align452alignment: 453legalized: true54regBankSelected: true55tracksRegLiveness: true56body: |57 bb.1.entry:58 ; MIPS32-LABEL: name: load_float_align459 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align460 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align461 ; MIPS32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load (s32) from @float_align4)62 ; MIPS32: $f0 = COPY [[LWC1_]]63 ; MIPS32: RetRA implicit $f064 %1:gprb(p0) = G_GLOBAL_VALUE @float_align465 %0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @float_align4)66 $f0 = COPY %0(s32)67 RetRA implicit $f068 69...70---71name: load_i32_align872alignment: 473legalized: true74regBankSelected: true75tracksRegLiveness: true76body: |77 bb.1.entry:78 ; MIPS32-LABEL: name: load_i32_align879 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align880 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align881 ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load (s32) from @i32_align8, align 8)82 ; MIPS32: $v0 = COPY [[LW]]83 ; MIPS32: RetRA implicit $v084 %1:gprb(p0) = G_GLOBAL_VALUE @i32_align885 %0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align8, align 8)86 $v0 = COPY %0(s32)87 RetRA implicit $v088 89...90