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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P56003--- |4 5 define void @sdiv_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }6 define void @sdiv_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }7 define void @sdiv_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }8 define void @sdiv_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }9 10 define void @srem_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }11 define void @srem_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }12 define void @srem_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }13 define void @srem_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }14 15 define void @udiv_v16u8(ptr %a, ptr %b, ptr %c) { entry: ret void }16 define void @udiv_v8u16(ptr %a, ptr %b, ptr %c) { entry: ret void }17 define void @udiv_v4u32(ptr %a, ptr %b, ptr %c) { entry: ret void }18 define void @udiv_v2u64(ptr %a, ptr %b, ptr %c) { entry: ret void }19 20 define void @urem_v16u8(ptr %a, ptr %b, ptr %c) { entry: ret void }21 define void @urem_v8u16(ptr %a, ptr %b, ptr %c) { entry: ret void }22 define void @urem_v4u32(ptr %a, ptr %b, ptr %c) { entry: ret void }23 define void @urem_v2u64(ptr %a, ptr %b, ptr %c) { entry: ret void }24 25...26---27name: sdiv_v16i828alignment: 429legalized: true30regBankSelected: true31tracksRegLiveness: true32body: |33 bb.1.entry:34 liveins: $a0, $a1, $a235 36 ; P5600-LABEL: name: sdiv_v16i837 ; P5600: liveins: $a0, $a1, $a238 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a039 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a140 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a241 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)42 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)43 ; P5600: [[DIV_S_B:%[0-9]+]]:msa128b = DIV_S_B [[LD_B]], [[LD_B1]]44 ; P5600: ST_B [[DIV_S_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)45 ; P5600: RetRA46 %0:gprb(p0) = COPY $a047 %1:gprb(p0) = COPY $a148 %2:gprb(p0) = COPY $a249 %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)50 %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)51 %5:fprb(<16 x s8>) = G_SDIV %3, %452 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)53 RetRA54 55...56---57name: sdiv_v8i1658alignment: 459legalized: true60regBankSelected: true61tracksRegLiveness: true62body: |63 bb.1.entry:64 liveins: $a0, $a1, $a265 66 ; P5600-LABEL: name: sdiv_v8i1667 ; P5600: liveins: $a0, $a1, $a268 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a069 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a170 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a271 ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)72 ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)73 ; P5600: [[DIV_S_H:%[0-9]+]]:msa128h = DIV_S_H [[LD_H]], [[LD_H1]]74 ; P5600: ST_H [[DIV_S_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)75 ; P5600: RetRA76 %0:gprb(p0) = COPY $a077 %1:gprb(p0) = COPY $a178 %2:gprb(p0) = COPY $a279 %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)80 %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)81 %5:fprb(<8 x s16>) = G_SDIV %3, %482 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)83 RetRA84 85...86---87name: sdiv_v4i3288alignment: 489legalized: true90regBankSelected: true91tracksRegLiveness: true92body: |93 bb.1.entry:94 liveins: $a0, $a1, $a295 96 ; P5600-LABEL: name: sdiv_v4i3297 ; P5600: liveins: $a0, $a1, $a298 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a099 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1100 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2101 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)102 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)103 ; P5600: [[DIV_S_W:%[0-9]+]]:msa128w = DIV_S_W [[LD_W]], [[LD_W1]]104 ; P5600: ST_W [[DIV_S_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)105 ; P5600: RetRA106 %0:gprb(p0) = COPY $a0107 %1:gprb(p0) = COPY $a1108 %2:gprb(p0) = COPY $a2109 %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)110 %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)111 %5:fprb(<4 x s32>) = G_SDIV %3, %4112 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)113 RetRA114 115...116---117name: sdiv_v2i64118alignment: 4119legalized: true120regBankSelected: true121tracksRegLiveness: true122body: |123 bb.1.entry:124 liveins: $a0, $a1, $a2125 126 ; P5600-LABEL: name: sdiv_v2i64127 ; P5600: liveins: $a0, $a1, $a2128 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0129 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1130 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2131 ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)132 ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)133 ; P5600: [[DIV_S_D:%[0-9]+]]:msa128d = DIV_S_D [[LD_D]], [[LD_D1]]134 ; P5600: ST_D [[DIV_S_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)135 ; P5600: RetRA136 %0:gprb(p0) = COPY $a0137 %1:gprb(p0) = COPY $a1138 %2:gprb(p0) = COPY $a2139 %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)140 %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)141 %5:fprb(<2 x s64>) = G_SDIV %3, %4142 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)143 RetRA144 145...146---147name: srem_v16i8148alignment: 4149legalized: true150regBankSelected: true151tracksRegLiveness: true152body: |153 bb.1.entry:154 liveins: $a0, $a1, $a2155 156 ; P5600-LABEL: name: srem_v16i8157 ; P5600: liveins: $a0, $a1, $a2158 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0159 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1160 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2161 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)162 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)163 ; P5600: [[MOD_S_B:%[0-9]+]]:msa128b = MOD_S_B [[LD_B]], [[LD_B1]]164 ; P5600: ST_B [[MOD_S_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)165 ; P5600: RetRA166 %0:gprb(p0) = COPY $a0167 %1:gprb(p0) = COPY $a1168 %2:gprb(p0) = COPY $a2169 %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)170 %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)171 %5:fprb(<16 x s8>) = G_SREM %3, %4172 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)173 RetRA174 175...176---177name: srem_v8i16178alignment: 4179legalized: true180regBankSelected: true181tracksRegLiveness: true182body: |183 bb.1.entry:184 liveins: $a0, $a1, $a2185 186 ; P5600-LABEL: name: srem_v8i16187 ; P5600: liveins: $a0, $a1, $a2188 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0189 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1190 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2191 ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)192 ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)193 ; P5600: [[MOD_S_H:%[0-9]+]]:msa128h = MOD_S_H [[LD_H]], [[LD_H1]]194 ; P5600: ST_H [[MOD_S_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)195 ; P5600: RetRA196 %0:gprb(p0) = COPY $a0197 %1:gprb(p0) = COPY $a1198 %2:gprb(p0) = COPY $a2199 %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)200 %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)201 %5:fprb(<8 x s16>) = G_SREM %3, %4202 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)203 RetRA204 205...206---207name: srem_v4i32208alignment: 4209legalized: true210regBankSelected: true211tracksRegLiveness: true212body: |213 bb.1.entry:214 liveins: $a0, $a1, $a2215 216 ; P5600-LABEL: name: srem_v4i32217 ; P5600: liveins: $a0, $a1, $a2218 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0219 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1220 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2221 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)222 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)223 ; P5600: [[MOD_S_W:%[0-9]+]]:msa128w = MOD_S_W [[LD_W]], [[LD_W1]]224 ; P5600: ST_W [[MOD_S_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)225 ; P5600: RetRA226 %0:gprb(p0) = COPY $a0227 %1:gprb(p0) = COPY $a1228 %2:gprb(p0) = COPY $a2229 %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)230 %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)231 %5:fprb(<4 x s32>) = G_SREM %3, %4232 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)233 RetRA234 235...236---237name: srem_v2i64238alignment: 4239legalized: true240regBankSelected: true241tracksRegLiveness: true242body: |243 bb.1.entry:244 liveins: $a0, $a1, $a2245 246 ; P5600-LABEL: name: srem_v2i64247 ; P5600: liveins: $a0, $a1, $a2248 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0249 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1250 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2251 ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)252 ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)253 ; P5600: [[MOD_S_D:%[0-9]+]]:msa128d = MOD_S_D [[LD_D]], [[LD_D1]]254 ; P5600: ST_D [[MOD_S_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)255 ; P5600: RetRA256 %0:gprb(p0) = COPY $a0257 %1:gprb(p0) = COPY $a1258 %2:gprb(p0) = COPY $a2259 %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)260 %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)261 %5:fprb(<2 x s64>) = G_SREM %3, %4262 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)263 RetRA264 265...266---267name: udiv_v16u8268alignment: 4269legalized: true270regBankSelected: true271tracksRegLiveness: true272body: |273 bb.1.entry:274 liveins: $a0, $a1, $a2275 276 ; P5600-LABEL: name: udiv_v16u8277 ; P5600: liveins: $a0, $a1, $a2278 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0279 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1280 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2281 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)282 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)283 ; P5600: [[DIV_U_B:%[0-9]+]]:msa128b = DIV_U_B [[LD_B]], [[LD_B1]]284 ; P5600: ST_B [[DIV_U_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)285 ; P5600: RetRA286 %0:gprb(p0) = COPY $a0287 %1:gprb(p0) = COPY $a1288 %2:gprb(p0) = COPY $a2289 %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)290 %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)291 %5:fprb(<16 x s8>) = G_UDIV %3, %4292 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)293 RetRA294 295...296---297name: udiv_v8u16298alignment: 4299legalized: true300regBankSelected: true301tracksRegLiveness: true302body: |303 bb.1.entry:304 liveins: $a0, $a1, $a2305 306 ; P5600-LABEL: name: udiv_v8u16307 ; P5600: liveins: $a0, $a1, $a2308 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0309 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1310 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2311 ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)312 ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)313 ; P5600: [[DIV_U_H:%[0-9]+]]:msa128h = DIV_U_H [[LD_H]], [[LD_H1]]314 ; P5600: ST_H [[DIV_U_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)315 ; P5600: RetRA316 %0:gprb(p0) = COPY $a0317 %1:gprb(p0) = COPY $a1318 %2:gprb(p0) = COPY $a2319 %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)320 %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)321 %5:fprb(<8 x s16>) = G_UDIV %3, %4322 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)323 RetRA324 325...326---327name: udiv_v4u32328alignment: 4329legalized: true330regBankSelected: true331tracksRegLiveness: true332body: |333 bb.1.entry:334 liveins: $a0, $a1, $a2335 336 ; P5600-LABEL: name: udiv_v4u32337 ; P5600: liveins: $a0, $a1, $a2338 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0339 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1340 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2341 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)342 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)343 ; P5600: [[DIV_U_W:%[0-9]+]]:msa128w = DIV_U_W [[LD_W]], [[LD_W1]]344 ; P5600: ST_W [[DIV_U_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)345 ; P5600: RetRA346 %0:gprb(p0) = COPY $a0347 %1:gprb(p0) = COPY $a1348 %2:gprb(p0) = COPY $a2349 %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)350 %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)351 %5:fprb(<4 x s32>) = G_UDIV %3, %4352 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)353 RetRA354 355...356---357name: udiv_v2u64358alignment: 4359legalized: true360regBankSelected: true361tracksRegLiveness: true362body: |363 bb.1.entry:364 liveins: $a0, $a1, $a2365 366 ; P5600-LABEL: name: udiv_v2u64367 ; P5600: liveins: $a0, $a1, $a2368 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0369 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1370 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2371 ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)372 ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)373 ; P5600: [[DIV_U_D:%[0-9]+]]:msa128d = DIV_U_D [[LD_D]], [[LD_D1]]374 ; P5600: ST_D [[DIV_U_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)375 ; P5600: RetRA376 %0:gprb(p0) = COPY $a0377 %1:gprb(p0) = COPY $a1378 %2:gprb(p0) = COPY $a2379 %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)380 %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)381 %5:fprb(<2 x s64>) = G_UDIV %3, %4382 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)383 RetRA384 385...386---387name: urem_v16u8388alignment: 4389legalized: true390regBankSelected: true391tracksRegLiveness: true392body: |393 bb.1.entry:394 liveins: $a0, $a1, $a2395 396 ; P5600-LABEL: name: urem_v16u8397 ; P5600: liveins: $a0, $a1, $a2398 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0399 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1400 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2401 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load (<16 x s8>) from %ir.a)402 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load (<16 x s8>) from %ir.b)403 ; P5600: [[MOD_U_B:%[0-9]+]]:msa128b = MOD_U_B [[LD_B]], [[LD_B1]]404 ; P5600: ST_B [[MOD_U_B]], [[COPY2]], 0 :: (store (<16 x s8>) into %ir.c)405 ; P5600: RetRA406 %0:gprb(p0) = COPY $a0407 %1:gprb(p0) = COPY $a1408 %2:gprb(p0) = COPY $a2409 %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)410 %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)411 %5:fprb(<16 x s8>) = G_UREM %3, %4412 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)413 RetRA414 415...416---417name: urem_v8u16418alignment: 4419legalized: true420regBankSelected: true421tracksRegLiveness: true422body: |423 bb.1.entry:424 liveins: $a0, $a1, $a2425 426 ; P5600-LABEL: name: urem_v8u16427 ; P5600: liveins: $a0, $a1, $a2428 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0429 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1430 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2431 ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load (<8 x s16>) from %ir.a)432 ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load (<8 x s16>) from %ir.b)433 ; P5600: [[MOD_U_H:%[0-9]+]]:msa128h = MOD_U_H [[LD_H]], [[LD_H1]]434 ; P5600: ST_H [[MOD_U_H]], [[COPY2]], 0 :: (store (<8 x s16>) into %ir.c)435 ; P5600: RetRA436 %0:gprb(p0) = COPY $a0437 %1:gprb(p0) = COPY $a1438 %2:gprb(p0) = COPY $a2439 %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)440 %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)441 %5:fprb(<8 x s16>) = G_UREM %3, %4442 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)443 RetRA444 445...446---447name: urem_v4u32448alignment: 4449legalized: true450regBankSelected: true451tracksRegLiveness: true452body: |453 bb.1.entry:454 liveins: $a0, $a1, $a2455 456 ; P5600-LABEL: name: urem_v4u32457 ; P5600: liveins: $a0, $a1, $a2458 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0459 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1460 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2461 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)462 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)463 ; P5600: [[MOD_U_W:%[0-9]+]]:msa128w = MOD_U_W [[LD_W]], [[LD_W1]]464 ; P5600: ST_W [[MOD_U_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)465 ; P5600: RetRA466 %0:gprb(p0) = COPY $a0467 %1:gprb(p0) = COPY $a1468 %2:gprb(p0) = COPY $a2469 %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)470 %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)471 %5:fprb(<4 x s32>) = G_UREM %3, %4472 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)473 RetRA474 475...476---477name: urem_v2u64478alignment: 4479legalized: true480regBankSelected: true481tracksRegLiveness: true482body: |483 bb.1.entry:484 liveins: $a0, $a1, $a2485 486 ; P5600-LABEL: name: urem_v2u64487 ; P5600: liveins: $a0, $a1, $a2488 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0489 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1490 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2491 ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)492 ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)493 ; P5600: [[MOD_U_D:%[0-9]+]]:msa128d = MOD_U_D [[LD_D]], [[LD_D1]]494 ; P5600: ST_D [[MOD_U_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)495 ; P5600: RetRA496 %0:gprb(p0) = COPY $a0497 %1:gprb(p0) = COPY $a1498 %2:gprb(p0) = COPY $a2499 %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)500 %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)501 %5:fprb(<2 x s64>) = G_UREM %3, %4502 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)503 RetRA504 505...506