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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP323# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP644--- |5 6 define void @i32tof32() {entry: ret void}7 define void @i32tof64() {entry: ret void}8 define void @u32tof64() {entry: ret void}9 10...11---12name: i32tof3213alignment: 414legalized: true15regBankSelected: true16tracksRegLiveness: true17body: |18 bb.1.entry:19 liveins: $a020 21 ; FP32-LABEL: name: i32tof3222 ; FP32: liveins: $a023 ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a024 ; FP32: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]25 ; FP32: $f0 = COPY [[PseudoCVT_S_W]]26 ; FP32: RetRA implicit $f027 ; FP64-LABEL: name: i32tof3228 ; FP64: liveins: $a029 ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a030 ; FP64: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]31 ; FP64: $f0 = COPY [[PseudoCVT_S_W]]32 ; FP64: RetRA implicit $f033 %0:gprb(s32) = COPY $a034 %1:fprb(s32) = G_SITOFP %0(s32)35 $f0 = COPY %1(s32)36 RetRA implicit $f037 38...39---40name: i32tof6441alignment: 442legalized: true43regBankSelected: true44tracksRegLiveness: true45body: |46 bb.1.entry:47 liveins: $a048 49 ; FP32-LABEL: name: i32tof6450 ; FP32: liveins: $a051 ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a052 ; FP32: [[PseudoCVT_D32_W:%[0-9]+]]:afgr64 = PseudoCVT_D32_W [[COPY]]53 ; FP32: $d0 = COPY [[PseudoCVT_D32_W]]54 ; FP32: RetRA implicit $d055 ; FP64-LABEL: name: i32tof6456 ; FP64: liveins: $a057 ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a058 ; FP64: [[PseudoCVT_D64_W:%[0-9]+]]:fgr64 = PseudoCVT_D64_W [[COPY]]59 ; FP64: $d0 = COPY [[PseudoCVT_D64_W]]60 ; FP64: RetRA implicit $d061 %0:gprb(s32) = COPY $a062 %1:fprb(s64) = G_SITOFP %0(s32)63 $d0 = COPY %1(s64)64 RetRA implicit $d065 66...67---68name: u32tof6469alignment: 470legalized: true71regBankSelected: true72tracksRegLiveness: true73body: |74 bb.1.entry:75 liveins: $a076 77 ; FP32-LABEL: name: u32tof6478 ; FP32: liveins: $a079 ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a080 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 1720081 ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 [[COPY]], [[LUi]]82 ; FP32: [[LUi1:%[0-9]+]]:gpr32 = LUi 1720083 ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 084 ; FP32: [[BuildPairF64_1:%[0-9]+]]:afgr64 = BuildPairF64 [[ORi]], [[LUi1]]85 ; FP32: [[FSUB_D32_:%[0-9]+]]:afgr64 = FSUB_D32 [[BuildPairF64_]], [[BuildPairF64_1]]86 ; FP32: $d0 = COPY [[FSUB_D32_]]87 ; FP32: RetRA implicit $d088 ; FP64-LABEL: name: u32tof6489 ; FP64: liveins: $a090 ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a091 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 1720092 ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64 = BuildPairF64_64 [[COPY]], [[LUi]]93 ; FP64: [[LUi1:%[0-9]+]]:gpr32 = LUi 1720094 ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 095 ; FP64: [[BuildPairF64_64_1:%[0-9]+]]:fgr64 = BuildPairF64_64 [[ORi]], [[LUi1]]96 ; FP64: [[FSUB_D64_:%[0-9]+]]:fgr64 = FSUB_D64 [[BuildPairF64_64_]], [[BuildPairF64_64_1]]97 ; FP64: $d0 = COPY [[FSUB_D64_]]98 ; FP64: RetRA implicit $d099 %0:gprb(s32) = COPY $a0100 %2:gprb(s32) = G_CONSTANT i32 1127219200101 %3:fprb(s64) = G_MERGE_VALUES %0(s32), %2(s32)102 %4:fprb(s64) = G_FCONSTANT double 0x4330000000000000103 %1:fprb(s64) = G_FSUB %3, %4104 $d0 = COPY %1(s64)105 RetRA implicit $d0106 107...108