100 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS323--- |4 5 @float_align1 = common global float 0.000000e+00, align 16 @float_align4 = common global float 0.000000e+00, align 47 @i32_align8 = common global i32 0, align 88 9 define void @store_float_align1(float %a) {10 entry:11 store float %a, ptr @float_align1, align 112 ret void13 }14 15 define void @store_float_align4(float %a) {16 entry:17 store float %a, ptr @float_align4, align 418 ret void19 }20 21 define void @store_i32_align8(i32 signext %a) {22 entry:23 store i32 %a, ptr @i32_align8, align 824 ret void25 }26 27...28---29name: store_float_align130alignment: 431legalized: true32regBankSelected: true33tracksRegLiveness: true34body: |35 bb.1.entry:36 liveins: $f1237 38 ; MIPS32-LABEL: name: store_float_align139 ; MIPS32: liveins: $f1240 ; MIPS32: [[COPY:%[0-9]+]]:fgr32 = COPY $f1241 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align142 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align143 ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]44 ; MIPS32: SWL [[COPY1]], [[ADDiu]], 3 :: (store (s32) into @float_align1, align 1)45 ; MIPS32: SWR [[COPY1]], [[ADDiu]], 0 :: (store (s32) into @float_align1, align 1)46 ; MIPS32: RetRA47 %0:fprb(s32) = COPY $f1248 %1:gprb(p0) = G_GLOBAL_VALUE @float_align149 %2:gprb(s32) = COPY %0(s32)50 G_STORE %2(s32), %1(p0) :: (store (s32) into @float_align1, align 1)51 RetRA52 53...54---55name: store_float_align456alignment: 457legalized: true58regBankSelected: true59tracksRegLiveness: true60body: |61 bb.1.entry:62 liveins: $f1263 64 ; MIPS32-LABEL: name: store_float_align465 ; MIPS32: liveins: $f1266 ; MIPS32: [[COPY:%[0-9]+]]:fgr32 = COPY $f1267 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align468 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align469 ; MIPS32: SWC1 [[COPY]], [[ADDiu]], 0 :: (store (s32) into @float_align4)70 ; MIPS32: RetRA71 %0:fprb(s32) = COPY $f1272 %1:gprb(p0) = G_GLOBAL_VALUE @float_align473 G_STORE %0(s32), %1(p0) :: (store (s32) into @float_align4)74 RetRA75 76...77---78name: store_i32_align879alignment: 480legalized: true81regBankSelected: true82tracksRegLiveness: true83body: |84 bb.1.entry:85 liveins: $a086 87 ; MIPS32-LABEL: name: store_i32_align888 ; MIPS32: liveins: $a089 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a090 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align891 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align892 ; MIPS32: SW [[COPY]], [[ADDiu]], 0 :: (store (s32) into @i32_align8, align 8)93 ; MIPS32: RetRA94 %0:gprb(s32) = COPY $a095 %1:gprb(p0) = G_GLOBAL_VALUE @i32_align896 G_STORE %0(s32), %1(p0) :: (store (s32) into @i32_align8, align 8)97 RetRA98 99...100