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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS323--- |4 5 define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void}6 define void @load2_s16_to_zextLoad2_s32(ptr %px) {entry: ret void}7 define void @load1_s8_to_sextLoad1_s32(ptr %px) {entry: ret void}8 define void @load2_s16_to_sextLoad2_s32(ptr %px) {entry: ret void}9 10...11---12name: load1_s8_to_zextLoad1_s3213alignment: 414legalized: true15regBankSelected: true16tracksRegLiveness: true17body: |18 bb.1.entry:19 liveins: $a020 21 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s3222 ; MIPS32: liveins: $a023 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a024 ; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY]], 0 :: (load (s8) from %ir.px)25 ; MIPS32: $v0 = COPY [[LBu]]26 ; MIPS32: RetRA implicit $v027 %0:gprb(p0) = COPY $a028 %2:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)29 $v0 = COPY %2(s32)30 RetRA implicit $v031 32...33---34name: load2_s16_to_zextLoad2_s3235alignment: 436legalized: true37regBankSelected: true38tracksRegLiveness: true39body: |40 bb.1.entry:41 liveins: $a042 43 ; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s3244 ; MIPS32: liveins: $a045 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a046 ; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY]], 0 :: (load (s16) from %ir.px)47 ; MIPS32: $v0 = COPY [[LHu]]48 ; MIPS32: RetRA implicit $v049 %0:gprb(p0) = COPY $a050 %2:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)51 $v0 = COPY %2(s32)52 RetRA implicit $v053 54...55---56name: load1_s8_to_sextLoad1_s3257alignment: 458legalized: true59regBankSelected: true60tracksRegLiveness: true61body: |62 bb.1.entry:63 liveins: $a064 65 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s3266 ; MIPS32: liveins: $a067 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a068 ; MIPS32: [[LB:%[0-9]+]]:gpr32 = LB [[COPY]], 0 :: (load (s8) from %ir.px)69 ; MIPS32: $v0 = COPY [[LB]]70 ; MIPS32: RetRA implicit $v071 %0:gprb(p0) = COPY $a072 %2:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)73 $v0 = COPY %2(s32)74 RetRA implicit $v075 76...77---78name: load2_s16_to_sextLoad2_s3279alignment: 480legalized: true81regBankSelected: true82tracksRegLiveness: true83body: |84 bb.1.entry:85 liveins: $a086 87 ; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s3288 ; MIPS32: liveins: $a089 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a090 ; MIPS32: [[LH:%[0-9]+]]:gpr32 = LH [[COPY]], 0 :: (load (s16) from %ir.px)91 ; MIPS32: $v0 = COPY [[LH]]92 ; MIPS32: RetRA implicit $v093 %0:gprb(p0) = COPY $a094 %2:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)95 $v0 = COPY %2(s32)96 RetRA implicit $v097 98...99